工作項目：

1. Familiar with Verilog design
2. Familiar with digital design flow, such as synthesis, STA, power analysis
3. Familiar with Video Codec (H.264, HEVC, AVS2, VP9, AV1…etc)
4. Familiar with at least one of following tasks
* DSP/processor design
* Design for Arithmetic operations
* Bus interface or fabric design
* SoC Design integration
* Image/video processing related design
* CPU/GPU/NPU experiences
* Communication and demodulation related design
* High Speed IO and DDR Memory controller


應徵條件：
1. 碩士以上;電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程、其他[理工背景]相關科系畢業為主
2. 熟悉 verilog, verdi, LEC, spyglass, perl, STA, synthesis tool
3. 不拘, 有二年以上工作經驗更好. 以上軟體不必全熟, 知道愈多愈好. 相關經驗者為佳。