ASIC Engineer (新竹)

1. Writing testbench and /or run mix-mode simulation.

2. Writing sensor timing control HDL code.

3. ISP(Image Signal Processing) development, HDL code and model.

4. Familiar with system-verilog is a plus.

5. Familiar with EDA tool is a plus(DC/PTIME/FORMAL/TESSENT/…)

6. Familiar with Customsim(XA) or Finesim is a plus.

7. Familiar with Xilinx FPGA development(design & debugging) is plus.