This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application.
* Studying and developing RTL code using VHDL or Verilog to accelerator kernels for Big Data platforms
* System debug & Validation of FPGA prototype systems
* Performance analysis and tuning of workloads on heterogeneous platform...