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Logo of 新加坡商鈦坦科技.
學習、向上提升,你就是我們的主角。 謝絕想要來安穩吃大鍋飯的高材生,歡迎有【熱忱】, 【追求極致】, 【樂於團隊合作】的夥伴一同打造一流的服務! 【工作內容】 1. Plan/Design/Maintain application servers on Physical servers, Private Cloud, Public Cloud to provide worldwide 24
網路管理工程師
系統維護/操作人員
資訊設備管制人員
60K ~ 90K TWD / month
4 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
Logo of 聖文森商瑞德克斯科技有限公司台灣分公司.
作及設定 (必備) 5. 熟悉軟體系統架構 (必備) 6. 熟悉多執行緒程式開發 (必備) 7. 熟悉T-SQL語法 (必備) 8. 熟悉Web Application相關技術,如HTML、CSS、AJAX、Javascript等 (必備) 9. 了解Design Pattern ※Job requirements 1. Good sense of logic and communication skills 2. A
40K ~ 80K TWD / month
1 years of experience required
No management responsibility
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Experience with RTL, low power (UPF/CPF), gate level (GLS) and formal
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or relat
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Experience with CPU or AI accelerator
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, a related technical field, or equivalent practical experience. 5 years of experience with software development in one or more programming languages, and with data structures/algorithms. 3 years of experience testing, maintaining, or launching software products, and 1 year of experience with software design and architecture. 3 years of experience with performance analys
Regular earnings reach NT$40,000
Logo of L'Oreal Malaysia.
END TO END PROCESS New store opening, renovation, revamping, temporary site including podiums/event Capable on proposing designs according to brand & location Brand staging according to marketing calendar Update planogram for all POS on time Co-ordinate with internal & external parties for all projects Check & work on site to ensure site readiness when required Responsible for P2P, including RFQ, AUC creation, settlement in system, end to end asset tagging etc DRIVE RETAIL DESIGN EXCELLENCE Work
5 years of experience required
Managing staff numbers: not specified
Logo of Google.
Google welcomes people with disabilities. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Taipei, Taiwan . Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. Experience verifying digital logic at RTL using SystemVerilog for ASICs. Experience verifying digital systems using standard IP componen
Logo of CakeResume Headhunting Recruitment Service.
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh
SystemC
RTL
SOC
3M ~ 4M TWD / year
10 years of experience required
No management responsibility

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