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Mid-Senior level
Logo of 浦飛爾科技有限公司.
1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
780K ~ 2.34M TWD / year
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus
Digital IC Designer
IC design
Memory
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
Logo of Morgan Philips Group.
Job Responsibilities: Engage in RTL/Digital circuit design, synthesis, and simulation/verification. Conduct FPGA synthesis and verification processes. Manage chip integration, algorithm implementation, and interface design. Generate test patterns.
1M ~ 3M TWD / year
3 years of experience required
No management responsibility
Logo of 緯創資通股份有限公司.
1. FPGA Development for server or communication applications , including IC design , Verilog coding , Simulation , Timing closure , Debug and Project maintenance. 2. Validate and Debug FPGA on prototype hardware system. 3. Co-work with Hardware and Software engineers in development. 4. Design tools implementation
Electronics Industry
40K ~ 60K TWD / month
2 years of experience required
No management responsibility
Logo of Ali Tech.
1.Front-End/Modem (Baseband) Architecture Design for WiFi6/BT/BLE systems; 2.Optimization of Frontend/Modem circuits and simulation/verifications; 3.Digital Circuit Design and Verification – RTL Coding/Synthesis/STA/…
C++
FPGA
ASIC
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of Ali Tech.
1.高速介面(SerDes)類比電路設計 2.Circuit design of CTLE/CDR/DFE/PLL/TX 3.Familiar with SerDes and DDR PHY architecture (ex: PCIe3 / USB3 / HDMI2 / DDR4 / LPDDR4/4x ...etc)
C++
FPGA
PLL
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of Ali Tech.
1. 具Bluetooth系統設計分析 2. Bluetooth產品設計專案規劃 3. 專案開發技術指導 4. 客戶參訪,技術方案支持及推廣
C++
Verilog
FPGA
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Analog & Digital Circuits Design AC/DC,DC/DC power design 使用OrCad 繪製電路圖,DC/DC Power Designing, 設計包含電流自檢, 電壓自檢, OCP, OVP, OTP等電路,電路控制CPLD/FPGA, 負責FCT 專案的研發, Wireless Board 的設計 與客戶溝通達到客戶產品測試
700K ~ 1.8M TWD / year
6 years of experience required
No management responsibility

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