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1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
IP Integration
IP Design
Digital IC
1.8M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
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1. Facilitate collaboration between foundries and teams in Japan or Taiwan. 2. Maintain seamless communication channels with foundries regarding CP/FT-related updates. 3. Track product yield performance across various technologies and provide reports to headquarters. 4. Collaborate with headquarters and foundries to identify strategies for improving product yield. 5. Troubleshoot issues during mass production and collaborate with headquarters and foundries to sustain yield levels. 6. Gather tech
Foundry
Product Engineer
IC Design
2M ~ 3.5M TWD / year
3 years of experience required
No management responsibility
Logo of NVIDIA.
NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team! The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/ . This
Verilog
TGC Europe
5 years of experience required
No management responsibility
Logo of NVIDIA.
We are now hiring for a Senior Mixed-signal Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can
Verilog
Mixed-Signal
PLL
5 years of experience required
No management responsibility
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1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh
SystemC
RTL
SOC
3M ~ 4M TWD / year
10 years of experience required
No management responsibility
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1. New Product CP/FT testing program development 2. Mass Production RMA analyzing, test pattern enhacement 3. CP probe card and FT load board out-sourcing manufacturing evaluation
Testing
Semiconductor
IC design
2M ~ 3.5M TWD / year
3 years of experience required
No management responsibility
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Developing products and enhancing yield through Foundry Effectively managing NPI issues across teams, ensuring timely coordination and leading the transition to mass production Producing well-organized characterization reports, meticulously analyzing data to identify strengths and weaknesses in mass production implementation Proficiently communicating with customers and vendors, adept at facilitating tasks across internal teams and external parties Conducting advanced process and vendor evaluati
Semiconductor
MP
NPI
2.5M ~ 4M TWD / year
10 years of experience required
No management responsibility
Logo of 宏正自動科技股份有限公司.
格及系統設計規劃。成為專業的數位 IC 研發工程師,與我們一同開創科技趨勢新局! 【工作內容】 As a IC Design Engineer, you will design, implement and verify products that use FPGAs and/or ASICs. 1. Participate in the micro architecture and design partition within the FPGAs and/or ASICs and implement design blocks using
40K ~ 80K TWD / month
No requirement for relevant working experience
No management responsibility
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參與SSD韌體專案開發,進行硬體控制器的設計和實現,以達到高性能和高可靠性的要求。 參與新功能的研發並進行性能評估,確保SSD韌體的不斷優化。 與HW Engineer 密切合作確保專案順利執行。
FTL
Firmware
SSD
2M ~ 3M TWD / year
2 years of experience required
No management responsibility
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2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility

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