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Logo of WASAI Technology.
* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform. * Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform. *You will join a growing team of digital IC design engineering professionals and have a real opportunity to have your hardware solutions
C
C++
OpenCL
80K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of WASAI Technology.
* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills
OpenCL
Verilog
VHDL
80K ~ 200K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 密碼演算法開發 2. 數位電路設計 (RTL) 3. 數位電路驗證 (UVM) 4. FPGA建置整合及驗證 -------------------------------------------------------------------------- 1. Crypto algorithm development 2. RTL design 3. UVM verification 4.
Linux
UNIX
40K+ TWD / month
3 years of experience required
No management responsibility
Logo of Ansys 安矽思科技股份有限公司.
SUMMARY The Application Engineer is responsible for providing world-class assistance to customers in the usage of RedHawk/RedHawk-SC, as well as for leveraging knowledge and relationships to assist in growing our software business in line with the corporate vision and performance expectations. Apply knowledge and experience in the areas of RTL design, custom circuit analysis, high-speed VLSI design, standard cell physical layout, power-grid extraction, timing analysis, noise analysis, and voltag
Regular earnings reach NT$40,000
3 years of experience required
No management responsibility
Logo of 智微科技股份有限公司.
1. Verify RTL design with System Verilog and UVM verification methodology. 2. PCIe or USB or SATA related VIP test maintenance and development. 3. Develop verification platform or behavioral models. 4.Test planning, testbench documentation and development.
Verilog
60K ~ 80K TWD / month
No management responsibility

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