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Logo of NVIDIA.
We are now looking for a ASIC Verification Engineer - Coherent High Speed Interconnect! For two decades, we have pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research. Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU
Testbenches
C++
PCIE
5 years of experience required
No management responsibility
Logo of NVIDIA.
NVIDIA is seeking outstanding entry-level Verification Engineers to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs by developing scalable testbench that is re-usable across different verification methodologies and environments. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing fiel
PCIE
ASIC
Verilog
2 years of experience required
No management responsibility
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or relat
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Experience with RTL, low power (UPF/CPF), gate level (GLS) and formal
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or relat
Regular earnings reach NT$40,000
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in design verification. Experience with functional verification and performance validation of modern mobile processors, microarchitecture, and related technologies. Experience developing and maintaining verification testbenches, test cases, and test environments. Prefer
Regular earnings reach NT$40,000
Logo of Andes Technology 晶心科技.
1. Verify RISC-V SOC platform including bus fabric, peripheral IPs: SPI, UART, I2C, PWM…etc. 2. Build testbench, develop and maintain in-house VIP 3. Create rand constraint conditions, analysis coverage holes and fill them 4. Create function coverage points to make sure all functions are under test
Verilog
C
C++
50K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 智微科技股份有限公司.
1. Verify RTL design with System Verilog and UVM verification methodology. 2. PCIe or USB or SATA related VIP test maintenance and development. 3. Develop verification platform or behavioral models. 4.Test planning, testbench documentation and development.
Verilog
60K ~ 80K TWD / month
No management responsibility

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