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【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計