CakeResume Job Search

Advanced filters
Off
Digital IC Design
Mid-Senior level
Logo of NVIDIA.
NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team! The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/ . This
Verilog
TGC Europe
5 years of experience required
No management responsibility
Logo of 台灣電子設計自動化股份有限公司.
TESDA, a fast growing startup is looking for manager with 5+ years experience and 1~5 digital design verification engineers. As a design verification engineer at TESDA, you'll be able to access and verify the design and implementation of hugely complex SoC from world class companies,attractive package and stock options. If you are looking for a position that can offer huge growth opportunity for career and personal finance and work-life balance, TESDA is the
Verilog
SystemVerilog
C/C++
80K ~ 200K TWD / month
5 years of experience required
Managing 5-10 staff
Logo of NVIDIA.
We are now looking for a Senior Research Scientist - Circuits. Advanced circuit design is critically important in the post-Moore’s Law age. Without the ability to scale process to increase performance and reduce power, we must rely more and more on creative architectural and underlying circuit solutions to provide continuing advancement from generation to generation. NVIDIA Research is seeking world-class circuit researchers to contribute to the exploration of future high-performance, low-power
Verilog
PLL
TGC Europe
No requirement for relevant working experience
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
Logo of 浦飛爾科技有限公司.
1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
780K ~ 2.34M TWD / year
No management responsibility

CakeResume Job Search

Join CakeResume now! Search tens of thousands of job listings to find your perfect job.