CakeResume Job Search

Analog IC Design
Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 類比電路開發設計與佈局優化(Bandgap, LDO, Charge Pump等類比電路) 2. 非揮發性記憶體電路開發設計(Array, Decoding, Sense Amplifier等電路) 3. 消費性、物聯網與車用電子之非揮發性記憶體電路整合開發設計 --------------------------------------------------------------------------------------------- Our Design Team is responsible for NVM (Non-Volatile Memory) IC circuit design. As an Analog Circuit Design Engineer, your responsibilities include: 1. Design, verify and debug analog circuits ( Bandgap, LDO, Charge Pum
40K+ TWD / month
No management responsibility
Logo of 印正有限公司 Yins Corp.
1.OPA,comparator design/verification 2.Bandgap,regulator design/verification 3.Charge pump design/verification 4.PLL,MIPI,oscillator design/verification 5.DAC/ADC design/verification 6.I/O,ESD design/verification 7.chip verification/debug
40K ~ 200K TWD / month
No management responsibility
Logo of 印正有限公司 Yins Corp.
1.OPA,comparator design/verification 2.Bandgap,regulator design/verification 3.Charge pump design/verification 4.PLL,MIPI,oscillator design/verification 5.DAC/ADC design/verification 6.I/O,ESD design/verification 7.chip verification/debug
40K ~ 200K TWD / month
2 years of experience required
No management responsibility
Logo of 工業技術研究院 (工研院,ITRI).
隨著晶片時代來臨,身為晶片人才或晶片專家的你,想為自己找尋一個創新的搖籃或挑戰嗎? 不論你是想投身前瞻晶片研究,或是想開發晶片相關的系統與軟韌體,最豐富與創新的資源就在工研院電光所!這裡有最夯的半導體研發、AI on Chip、量子電腦和晶片系統設計應用......等大型晶片前瞻計畫,等你一起來探索。 我們歡迎無經驗的新鮮人,也歡迎資深IC和相關系統人才,帶上你對晶片的熱情,一起在工研院電光所和我們共創晶片新世代!
40K ~ 100K TWD / month
No management responsibility
Logo of Realtek 瑞昱半導體.
1.高速 PLL 與 Serdes 的類比電路開發工作 2.負責Serdes PHY與PCIe/SATA PHY的開發與維護工作
PLL
Analog IC
Serdes
60K ~ 90K TWD / month
No management responsibility
Logo of 多方科技股份有限公司.
工作內容 (Job Description) -Analog design, such as ADC/DAC PLL or LDO 工作職責 (Responsibilities): -Build & innovate on mixed-signal circuits such as ADC/DAC PLL or LDO in deep sub-micron CMOS technology for integration in SoC products -Work with digital team on specification definition -Create behavior model for analog/digital evaluation -Compliance test for analog IP
1.2M ~ 2M TWD / year
1 years of experience required
No management responsibility
Logo of 多方科技股份有限公司.
工作職責 (Responsibilities): Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. Work with digital team on specification definition Create behavior model for analog/digital evaluation Compliance test for SerDes IP
Linus
1.2M ~ 2M TWD / year
1 years of experience required
No management responsibility
Logo of 晶豪科技 ESMT.
1. Design wireless SoC analogue building blocks. 2. Review design specification based on system requirements. 3. Communicate with baseband algorithm, RF system, device and layout teams. 4. Present topology studies, design consideration, simulation and verification plan. 5. Conduct lab measurement and report design-vs- silicon correlation. 6. Experience with any of the below is a plus •Wireless SoC development •LNA •Mixer •Amplifier •VCO •PLL •Baseband Filter •VGA •ADC •PMU •LDO •oscillator
60K ~ 200K TWD / month
3 years of experience required
No management responsibility
Logo of 晶豪科技 ESMT.
新竹 1. 電視及手機應用的 Audio IC相關晶片類比電路之開發。 2. 熟類比電路者。 3.熟悉Audio或電源管理IC應用與測試條件。 4.電源管理IC之規格及開發時程評估。 5.電源管理IC之IP電路開發、整合。 6.電源管理IC 之驗證及驗證問題解決。 7.電源管理IC 之量產前故障問題之分析。 8.提供電源管理IC 客訴時之專家意見。 台南 1. 電視及手機應用的 Audio IC相關晶片類比電路之開發。 2. 熟類比電路者。 3. 熟悉Audio應用及測試。 4. 電路的failure analysis. 5. 單獨IP模擬以及total 類比電路的wholechip simulation. 6. 具量產經驗者佳。
60K ~ 200K TWD / month
2 years of experience required
No management responsibility
Logo of Alpha & Omega Semiconductor (Taiwan) Ltd. .
1) DCDC Power IC design 2) Over 3~5 years experience in design house. power management is a must. 3) Review colleague's projects and own projects.
2M ~ 3M TWD / year
No management responsibility

CakeResume Job Search

Join CakeResume now! Search tens of thousands of job listings to find your perfect job.