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Digital IC Design
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1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
IP Integration
IP Design
Digital IC
1.8M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
Logo of NVIDIA.
NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team! The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/ . This
Verilog
TGC Europe
5 years of experience required
No management responsibility
Logo of NVIDIA.
We are now looking for a Research Scientist - Circuits - New College Graduate. Advanced circuit design is critically important in the post-Moore’s Law age. Without the ability to scale process to increase performance and reduce power, we must rely more and more on creative architectural and underlying circuit solutions to provide continuing advancement from generation to generation. NVIDIA Research is seeking world-class circuit researchers to contribute to the exploration of future high-perform
Verilog
PLL
TGC Europe
No requirement for relevant working experience
No management responsibility
Logo of NVIDIA.
We are now looking for a Senior Research Scientist - Circuits. Advanced circuit design is critically important in the post-Moore’s Law age. Without the ability to scale process to increase performance and reduce power, we must rely more and more on creative architectural and underlying circuit solutions to provide continuing advancement from generation to generation. NVIDIA Research is seeking world-class circuit researchers to contribute to the exploration of future high-performance, low-power
Verilog
PLL
TGC Europe
No requirement for relevant working experience
No management responsibility
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1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh
SystemC
RTL
SOC
3M ~ 4M TWD / year
10 years of experience required
No management responsibility
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻交易、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自
FPGA
Verilog
100K ~ 150K TWD / month
5 years of experience required
No management responsibility
Logo of 宏正自動科技股份有限公司.
你渴望在科技浪潮趨勢下,挑戰全球市場,創造新價值,成為卓越的數位 IC 研發工程師嗎? 宏正自動科技作為多電腦切換器KVM全球領導品牌,你將與全球夥伴交流,在國際環境中快速成長! 作為「儲備
40K ~ 80K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
IC Designer
Top integrator
SoC
1.8M ~ 3M TWD / year
1 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff

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