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Hsieh Azure
R&D process integration engineer
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Hsieh Azure

R&D process integration engineer
Graduated with a master's degree in Electrical Engineering Department from National Yang Ming Chiao Tung University. As a R&D process integration engineer in UMC about 7.7 years of experience; and process integration engineer in TSMC about 3.8 years of experience. Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement. Email : [email protected] Phone: 0910-828-616
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UMC
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National Yang Ming Chiao Tung University
Tainan, 台灣

Professional Background

  • Situación actual
    Desempleado
    No está abierto a oportunidades
  • Profession
    Electronics Engineer
    Process Engineer
    I&C Engineer
  • Fields
    Electrónica / Telecomunicaciones
    Nanotechnology
    Semiconductores
  • Experiencia laboral
    10-15 años (10-15 años relevante)
  • Management
    Ninguno
  • Skills
    Excel
    reliability
    Process Integration
    Yield Enhancement
    Failure Analysis
  • Languages
    English
    Intermedio
    Japanese
    Principiante
  • Highest level of education
    Master

Job search preferences

  • Desired job type
    A tiempo completo
    Interesado en trabajar a distancia
  • Desired positions
    Semiconductor Engineer
  • Lugares de trabajo deseados
    Tainan City, Taiwan
    Kaohsiung City, Taiwan
  • Freelance
    No freelance

Work Experience

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R&D process integration engineer

UMC
A tiempo completo
jun 2014 - mar 2022
7 yrs 10 mos
Tainan City, Taiwan
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement 1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process develop, yield ramp up and reliability improve. EM life time reach 10,000 years in 1000ppm for specify customer requested 2. BEoL interconnect (pitch 52nm, SADP-DUV) process develop, include rule and test key design 3. 22nm eHV (device operate in 8V-27V) interconnect process develop
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Process integration engineer

jul 2010 - abr 2014
3 yrs 10 mos
Tainan City, Taiwan
Process integration engineer in 40nm - 90nm mature technology 1. Customer handling ( include new tape-out, low yield analysis, WAT, SPC chart monitor...etc) 2. 20nm process transfer from Hsinchu to Tainan

Education

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Master’s Degree
Electrical Engineering & IC design
2006 - 2009
Descripción
Research topic: A Digital Calibration Scheme for the Successive Approximation Analog-to-Digital Converter
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Bachelor’s Degree
Electrical Engineering Department
2002 - 2006