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Hsieh Azure
R&D process integration engineer
Graduated with a master's degree in Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D process integration engineer in UMC about 7.7 years of experience; and process integration engineer in TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device
reliability improvement.
Email : [email protected]
Phone: 0910-828-616
UMC
National Yang Ming Chiao Tung University
Tainan, 台灣
Professional Background
- 現在の状況無職・就職を希望していません
- ProfessionElectronics Engineer・Process Engineer・I&C Engineer
- Fields電子・電気通信・Nanotechnology・半導体
- 職務経験10〜15年 (10〜15年関連の実務経験)
- Managementなし
- Skills
- LanguagesEnglish・中級者Japanese・初心者
- Highest level of educationMaster
Job search preferences
- Desired job typeフルタイム・リモートワークに興味あり
- Desired positionsSemiconductor Engineer
- 希望の勤務地Tainan City, Taiwan・Kaohsiung City, Taiwan
- Freelance非フリーランス
Work Experience
R&D process integration engineer
Tainan City, Taiwan
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process develop, yield ramp up and reliability improve. EM life time reach 10,000 years in 1000ppm for specify customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process develop, include rule and test key design
3. 22nm eHV (device operate in 8V-27V) interconnect process develop
Process integration engineer
Tainan City, Taiwan
Process integration engineer in 40nm - 90nm mature technology
1. Customer handling ( include new tape-out, low yield analysis, WAT, SPC chart monitor...etc)
2. 20nm process transfer from Hsinchu to Tainan
Education
Master’s Degree
・
Electrical Engineering & IC design詳細
Research topic: A Digital Calibration Scheme for the Successive Approximation Analog-to-Digital Converter
Bachelor’s Degree
・
Electrical Engineering Department