(TSMC Fab15B July 2017~ Nov 2018)
• FinFET ETC pi run/ramp up and key stage yield monitor
=> Ramp up key stage (SiGe/OD/POLY Loop) about WAT/YIELD, develop advanced process control to compensate even-odd issue.
• FEOL Stage and P-EPI,OD,POLY,FIN RECESS Loop sponsor
=>DOE research and recipe set up via experiment and theorem.
• Knowledge of AMAT tools and recipe tuning to gain yield 2%
=>Build a advanced recipe to improve yield about 2%.