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林京誼
Principal process Integration engineer
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林京誼

Principal process Integration engineer
Advanced package CoWoS principal engineer and integration engineer team leader. Specialized in NPI, HVM, reliability, yield and line quality maintaining. Previously R&D staff process integration engineer of 14 nm FinFET devices. Familiar with process flow design. Strong understanding of mechanical properties, devices (FinFET, power MOSFET). Capable of executing new packages to enhance electrical performance and yield.
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tsmc
Logo of the organization.
National Taiwan University
新竹市, 台灣

Featured Resume

Uploaded on May 12th 2024

Professional Background

  • Current status
    Employed
    Ready to interview
  • Profession
    Other
  • Fields
    Manufacturing
  • Work experience
    6-10 years (6-10 years relevant)
  • Management
    I've had experience in managing 5-10 people
  • Skills
    Team Player
    microsoft office suite
    Process Flow Design
    Process Integration
    Circuit Layout
    Device Physics
    Word
    Data Analysis
    DOE
    MOSFET
    FinFET
    FMEA 失效模式與效應分析
    CoWoS
    advanced packaging
    Supply Chain Management
    Team Management
    English
  • Languages
    English
    Professional
  • Highest level of education
    Master

Job search preferences

  • Desired job type
    Full-time
    Interested in working remotely
  • Desired positions
    Manager
  • Desired work locations
    Hsinchu City, Taiwan
  • Freelance
    Non-freelancer

Work Experience

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Principal Integration Engineer

tsmc
Full-time
Nov 2019 - Present
Longtan District, Taoyuan City, Taiwan
Hsinchu City, Taiwan
-Leader of 6-member process integration team -Collaboration with customers to design 20+ CoWoS packages and successful mass production -New 2.5D/3D technology introduction to ramping and production -Cross site supply chain management and yield maintain>99.5%
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Senior Process Integration Engineer

Oct 2015 - Oct 2019
4 yrs 1 mo
-FinFET platform circuit layout and process flow design -UMC's first FinFET product development and ramping -Charge mobility and silicon channel strain boost 5+% by dual epitaxial process -HK metal gate formation and dimensions design for device power control -Metal zero interconnect process robustness improvement, circuit open ratio decreased to < 1%

Education

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Master’s Degree
Master Degree of Chemical Engineering
2013 - 2015
4/5 GPA
Description
-Silicon sheet electric zone melting thermal and crystallization simulation by phase field model, with finite element method and adaptive mesh by Fortran -Poster exhibition at CSSC-8 (international workshop on crystalline silicon for solar cells) in Bamberg, Germany
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Bachelor’s Degree
Bachelor’s Degree of Chemistry and Chemical Engineering
2013 - 2015
3.6/5 GPA
Description
-Interdisciplinary degree of chemical engineering and chemistry