CakeResume Talent Search

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4〜6年
6〜10年
10〜15年
15年以上
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Past
R&D process integration engineer @ UMC
2014 ~ 2022
Semiconductor Engineer
1年以上
Excel
reliability
Process Integration
無職
就職を希望していません
フルタイム / リモートワークに興味あり
10〜15年
National Yang Ming Chiao Tung University
Electrical Engineering & IC design
Avatar of Ming-Yao (Mike), Chen.
Avatar of Ming-Yao (Mike), Chen.
External Manufacturing Manager @ONsemiconductor
2018 ~ 現在
Managing Director
1年以上
In process control (stability), process capability best practice cross fertilization management. • Promoting yield improvement and systematically feedback information to new product development team, PDCA cycle review. • Actively identify scrap saving opportunities. • Process optimization related to yield loss caused by strict customer requirements and quality case. • Be yield enhancement hub for technical assessment from IC circuit design, wafer manufacturing, assembly, test and OSAT capability evaluation. • Initiate taskforces to drive OSAT on multi-dimensional tasks including customer voice, quality focus, production sustaining. • Lead continuous improvement program to achieve excellent yield and quality performance. • Drive yield
word
powerpoint
Excel
就職中
フルタイム / リモートワークに興味あり
6〜10年
National Chiao Tung University, Hsinchu, Taiwan, Republic of China
Material Science and Engineering
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Past
研發工程師 @新日興股份有限公司
2021 ~ 2023
機械工程師,半導體製程工程師,半導體設備工程師,
1ヶ月以内
Word
PowerPoint
Excel
無職
面接の用意ができています
フルタイム / リモートワークに興味なし
6〜10年
國立台北科技大學
Materials Science and Engineering
Avatar of 吳明赫.
Avatar of 吳明赫.
Test Equipment Technician @Micron Technology 台灣美光
2018 ~ 現在
製程工程師、設備工程師、半導體工程師
1ヶ月以内
吳明赫 Test Equipment Technician Taichung City, Taiwan Passionate about continuous learning and professional growth, good at working effectively under pressure, with 10 years of experience in semiconductor back-end equipment. Demonstrates excellence in equipment maintenance, upkeep, improvements and capability enhancements. 工作經歷 Test Equipment Technician Micron Technology 台灣美光 • 十一月Present # Leadership Daily *improvement Equipment UPH/PPJ/MTBF/SDT/UDT KPI, until meet target *Mentor other equipment engineers in the respective area *Support edit/improve Equipment...OCAP/Procedure/SOP
Microsoft Office
critical thinking
Analytical Skills
就職中
面接の用意ができています
フルタイム / リモートワークに興味なし
10〜15年
南台科技大學
電機工程系
Avatar of shih-heng sun.
Avatar of shih-heng sun.
Past
Process Integration Engineer @TSMC Fab12B
2019 ~ 2021
Yield Improvement Engineer
1年以上
Shih Heng Sun Semiconductor Process Integration Engineer with 5+ years of experience. TSMC PIE specializing in advanced technology semiconductor products (3nm~10nm). Well-versed in yield improvement of semiconductor manufacturing process, Logic IC yield analysis, and collaborating with production line to solve problems. Making a huge leap for TSMC advanced IC fabrication in process integration and yield improvement. Enthusiastic about semiconductor product development and design which can change people's lives. Work Experiences Yield Improvement Engineer • TSMC Fab12B AugustDecember 2020 Expert in most advanced Logic IC process (5nm~10nm) and familiar with advanced measuring
Communicating
Measuring Instruments
Semiconductor Process
無職
フルタイム / リモートワークに興味あり
4〜6年
National Taiwan University
M.S. Photonics and Optoelectronics
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Avatar of the user.
Project Enginner @ASE Technology Holding Co., Ltd.
2019 ~ 現在
QA Engineer
1年以上
Word
Excel
PowerPoint
就職中
フルタイム / リモートワークに興味あり
6〜10年
國立嘉義大學
應用數學, 統計
Avatar of Wen Chun-I.
Avatar of Wen Chun-I.
Backend @胡了資訊
2023 ~ 現在
Software Engineer / Backend Engineer
1ヶ月以内
of about 50,000 players at the same time. 3.Designed a new poker game using .NET Core and also handled the system design. 4.Improved system performance when 30,000 players were online with 100 containers, each with 1 core CPU. Before the enhancement, the CPU loading was at 10%, but after the enhancement, the CPU loading was reduced to 1%. At the same time, used interpolation to reduce data transfer volume to 1/10 of the original data. 5.Promoted to a backend lead and job responsibilities included
Rust
Node.js
TypeScript
就職中
就職を希望していません
フルタイム / リモートワークに興味あり
6〜10年
Fju Jen Catholic University
Math

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6ヶ月以内
Product Device Engineer
Taiwan Semiconductor Manufacturing Company (TSMC)
2020 ~ 現在
Taiwan
Professional Background
現在の状況
就職中
求人検索の進捗
Professions
Product Engineer
Fields of Employment
半導体
職務経験
2〜4年
Management
I've had experience in managing 15+ people
スキル
WAT analysis
FinFET
Semiconductor Process
Yield analysis/enhancement
CMOS Technology
Electrical analysis
言語
English
ビジネスレベル
Chinese
ネイティブまたはバイリンガル
Job search preferences
希望のポジション
Product Device Engineer
求人タイプ
フルタイム
希望の勤務地
Hsinchu City, 台灣
リモートワーク
リモートワークに興味あり
Freelance
はい、私はアマチュアのフリーランスです。
学歴
学校
Tsinghua University
専攻
Master's degree Material Science
印刷

Shengzhe Hong

TSMC product engineer (Device team), involved in FinFET tech, such as N5/ N12/ N16.
Specialize in WAT analysis, be able to logically identify potential electrical problems.
In addition, I have good communication skills and rich experience in X-dep. work.
Extremely interested in companies located in Taipei/Hsinchu or the USA.

  Taiwan   

Experience

Product Device Engineer  •  Taiwan Semiconductor Manufacturing Company (TSMC)

Aug 2020 - Present · 1 yr 5 m, Tainan City, Taiwan

• N5 mass production owner by WAT analysis, find out the potential electrical abnormality.
• Device (RO%) boost by Speed/Iddq/Vts/Isat/DIBL/LC/SC/Sws tracking analysis.
• Customer handling, ex: HPC Project/ S2S/ Wafer uniformity improvement (IDU/VtU/SPU)/ S2S.
• Yield analysis (Mbist/ LVccmin/ IDS/ Repair/ Chain scan) to develop the yield loss spec.
• SPICE model setting/ corner skew methodology (FF/SS/FS/SF).
• Capacity improvement (WPH) check with the integration team.
• Reliability (RA) improvement (HTOL/ TDDB) BKM check with QR team.

Product Device Engineer  •  Taiwan Semiconductor Manufacturing Company (TSMC)

Sep. 2018 - July 2020

• N12/ N16 mass production (MP) owner by WAT analysis.
• Support Nanjing fab (F16) MP and NTO ramp-up/ RTO/ Corner split provider.
• Customer handling: RO%/Speed/Iddq boost by tuning process, like Poly/Fin/ EPI/ Metal gate.
N12/16 SPICE model setting: propose a reasonable SPICE target by estimating the future silicon. 
Co-work with TDID and SPICE model team to set up SPICE.

• Deeply understand the correlation between inline (process) and WAT index.

Education

Skills


  • WAT analysis/ FinFET
  • Semiconductor Process
  • Yield analysis/enhancement

Language


  • English — Excellent
  • Chinese — Native

2015 - 2018

Tsinghua University

Master's degree in Material Science

2011 - 2015

National Taipei University of Technology

Bachelor's degree in Material Science

Resume
プロフィール

Shengzhe Hong

TSMC product engineer (Device team), involved in FinFET tech, such as N5/ N12/ N16.
Specialize in WAT analysis, be able to logically identify potential electrical problems.
In addition, I have good communication skills and rich experience in X-dep. work.
Extremely interested in companies located in Taipei/Hsinchu or the USA.

  Taiwan   

Experience

Product Device Engineer  •  Taiwan Semiconductor Manufacturing Company (TSMC)

Aug 2020 - Present · 1 yr 5 m, Tainan City, Taiwan

• N5 mass production owner by WAT analysis, find out the potential electrical abnormality.
• Device (RO%) boost by Speed/Iddq/Vts/Isat/DIBL/LC/SC/Sws tracking analysis.
• Customer handling, ex: HPC Project/ S2S/ Wafer uniformity improvement (IDU/VtU/SPU)/ S2S.
• Yield analysis (Mbist/ LVccmin/ IDS/ Repair/ Chain scan) to develop the yield loss spec.
• SPICE model setting/ corner skew methodology (FF/SS/FS/SF).
• Capacity improvement (WPH) check with the integration team.
• Reliability (RA) improvement (HTOL/ TDDB) BKM check with QR team.

Product Device Engineer  •  Taiwan Semiconductor Manufacturing Company (TSMC)

Sep. 2018 - July 2020

• N12/ N16 mass production (MP) owner by WAT analysis.
• Support Nanjing fab (F16) MP and NTO ramp-up/ RTO/ Corner split provider.
• Customer handling: RO%/Speed/Iddq boost by tuning process, like Poly/Fin/ EPI/ Metal gate.
N12/16 SPICE model setting: propose a reasonable SPICE target by estimating the future silicon. 
Co-work with TDID and SPICE model team to set up SPICE.

• Deeply understand the correlation between inline (process) and WAT index.

Education

Skills


  • WAT analysis/ FinFET
  • Semiconductor Process
  • Yield analysis/enhancement

Language


  • English — Excellent
  • Chinese — Native

2015 - 2018

Tsinghua University

Master's degree in Material Science

2011 - 2015

National Taipei University of Technology

Bachelor's degree in Material Science