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On
4-6 years
6-10 years
10-15 years
More than 15 years
Active
Active
資深產品工程師 @Dialog Semiconductor 德商戴樂格半導體有限公司台灣分公司2022 ~ Present
・
工程師
Within one month
限流(Self-compliance) 的 3D結構RRAM ，並發表在 IOPscience 期刊 親自進無塵室操作多種 機台完成每道製程，清楚瞭解整套RRAM製程流程技能 半導體製程 半導體物理 半導體材料 電性分析 電性量測(DC/TLP SOA) 良率分析 資料統計分析 風險評估分析及應對策略擬定 BCD 製程
Employed
Full-time / Interested in working remotely
6-10 years
國立交通大學 National Chiao Tung University
・
電子工程
Unemployed
Full-time / Interested in working remotely
4-6 years
國立台灣科技大學
・
材料所製程工程師 @台灣美光記憶體股份有限公司2021 ~ Present
・
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
Within one month
Employed
・
Ready to interview
Full-time / Interested in working remotely
4-6 years
國立雲林科技大學
・
化學工程與材料工程
Past
製程工程師 @漢民科技股份有限公司2020 ~ 2023
・
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
Within one month
控與軟體工程師溝通協調，在有限的時間內協助客戶進行量產與教導客戶使用機台。 離開斯托克後，我來到漢民科技擔任製程工程師(R&D)，負責第三代半導體—碳化矽(SiC)的晶圓切割；這是一個我完全不懂得領域，我必須一邊進行摸索與了解這個
Unemployed
・
Ready to interview
Full-time / Interested in working remotely
4-6 years
國立台灣師範大學
・
化學
ERP資訊工程師-ERP Software Engineer @南茂科技股份有限公司 ChipMOS TECHNOLOGIES2022 ~ Present
・
Engineer, SA, SD, Data Analyst, PM
Within one month
項，其誤報率在10%以內，替聯電減少約2千萬的成本。 FDC UI系統以機台資料為主，系統偵錯在3個標準差之內，以及開發晶圓製程相關UI、資料分析與視覺化的功能。 程式效能與SQL效能減少平均約25%~75%的執行時間。 程式碼覆蓋率依據不同系統，平均
Employed
・
Open to opportunities
Full-time / Interested in working remotely
6-10 years
國立成功大學 National Cheng Kung University
・
Industrial and Information Management
Past
半導體製程工程師 @Visera 采鈺科技2022 ~ 2023
・
工程師、軟體工程師、高級工程師、
Within six months
時間提升專業知識並精進程式語言，在自動化領域約有5年資歷，希望未來可從事半導體、IC設計或外商設備商等工程師相關工作，如對我的資歷有興趣也可參考工作經歷與我的作品集，謝謝! Taichung City, Taiwan 工作經歷 半導體製程工程師 • Visera 采鈺科技 八
Unemployed
Full-time / Not interested in working remotely
4-6 years
國立中興大學
・
電機工程學系
Within six months
點。我擅於用不同角度思考問題，並在溝通與合作方面有著出色的表現。 【工作經驗】 1.目前於樂福太陽能擔任，太陽能電池製程工程師，負責物理真空蒸鍍機台製程與異常處理 2.曾在半導體產業的力積電做過擴散製程工程師 3.在南光化
Employed
Full-time / Not interested in working remotely
6-10 years
軟/韌體工程師 @北河精密機電有限公司2017 ~ 2023
・
軟/韌體工程師
Within one year
售市場。 (Microchip、STM32、ESP32、Arduino) 配合馬達控制器，進行桌面應用程式之設計與撰寫。(Qt C++、C#) 超過30間客戶的合作經驗，其領域包括：半導體製程機台、 醫療/復健用具 、電動螺絲刀、無人搬運車... 。 自動化相關領域實務操作經驗。(CANopen、etherCAT、RS485、PLC、AC driver...) 專
Employed
・
Not open to opportunities
Full-time / Interested in working remotely
4-6 years
亞東科技大學
・
通訊工程系Past
Senior Process Engineer @穩懋半導體股份有限公司2015 ~ 2021
・
Senior Engineer
More than one year
Unemployed
Full-time / Interested in working remotely
6-10 years
淡江大學 Tamkang University
・
化學工程學, 材料工程學
Past
製程工程師 @台灣積體電路公司2018 ~ 2020
・
研發工程師
Within six months
Language English - Fluent Taiwanese - Fluent Mandarin - Fluent 自傳 出生於1990年，台南人，射手座B型。 個性活潑外向，平時喜歡打羽球和騎腳踏車。 目前在找第三份研發/製程相關工作。 2015/11~2018/05 聯華電子蝕刻二部製程工程師 近三年的工作經歷在半導體業 期間除了維持製程上的穩定
Unemployed
Full-time / Interested in working remotely
4-6 years
成功大學
・
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Definition of Reputation Credits
Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
Communication
Ability to convey information effectively and is willing to give and receive feedback.
Time Management
Ability to prioritize tasks based on importance; and have them completed within the assigned timeline.
Teamwork
Ability to work cooperatively, communicate effectively, and anticipate each other's demands, resulting in coordinated collective action.
Leadership
Ability to coach, guide, and inspire a team to achieve a shared goal or outcome effectively.
Professional Background
Current status
Employed
Job Search Progress
Professions
Process Engineer
Fields of Employment
Semiconductor
Work experience
6-10 years
Management
None
Skills
Languages
English
・
Professional
Job search preferences
Positions
工程師
Job types
Full-time
Locations
台灣新竹市
Remote
Interested in working remotely
Freelance
No
Educations
School
國立交通大學 National Chiao Tung University
Major
電子工程
陳嘉豪
資深主任製程整合工程師
- 6年半導體製程經驗
- 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
- 掌管全廠最大量產品BCD
- 成功改善超過40餘起案件
- 完成2項公司A級專案
- 訂定超過60餘項最佳化條件(BKM)
- 熟悉多台機台操作
新竹縣竹北市
+886 0989-929-413
工作經歷
UMC 聯華電子 - 資深主任製程整合工程師
一月 2017 - Present (5年)
- 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
- 負責產品：BCD(全廠最大產量)、Logic
- 工作內容：
- 開發新平台(Platform)
- 改善跨製程問題
- WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
- 監控線上產品
- 導入新產品
- 客戶專案的推動 / 執行
- 回覆客戶問題及處理客訴
- 成就 / 貢獻：
- 成功改善40餘起案子，其中超過20項重大案件
- HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
- 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
- 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
- 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
- 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
- 熟悉多台機台操作
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
- 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定
- 成功改善40餘起案子，其中超過20項重大案件
碩士學歷
Micron 美光科技 - 高級缺陷改善工程師
一月 2016 - 十二月 2016 (1年)
- 負責產品：SI(Silicon interposer)
- 工作內容：
- 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
- 跨部門專案的推動 / 執行
- 跨部門合作改善缺陷數量
- 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 成就 / 貢獻：
- 成功解決影響全廠的Wafer edge low yield issue
- 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 熟悉SEM, EDS, Leica機台操作
國立交通大學 - 電子工程學研究所
國立中央大學 - 化學工程與材料工程學研究所
指導教授：侯拓宏, 周正堂 教授
GPA：3.8/4
期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)
實驗地點：國家實驗研究院(NARLabs)
成就 / 貢獻：
- 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
- 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程
2012 - 2014
2012 - 2014
技能
- 半導體製程
- 半導體物理
- 半導體材料
- 電性分析
- 電性量測(DC/TLP SOA)
- 良率分析
- 資料統計分析
- 風險評估分析及應對策略擬定
- BCD 製程
- BCD 元件分析
擅長工具
Excel PowerPoint Word
語言
- 中文
- 英文 - TOEIC：760
Jia-Hao Chen
Senior Principal Process Integration Engineer(PIE)
- 6 years' experience in semiconductor field
- Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- In charge of the product BCD with maximum output in the whole factory
- Successfully improved more than 40 cases
- Finished 2 of our company's top projects
- Defined more than 60 best known methods(BKM)
- Specialize in operating numerous equipment
Hsinchu, Taiwan
+886 0989-929-413
Work Experience
UMC - Senior Principal Process Integration Engineer
Jan., 2017 - Present (5 Years)
- Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- Product：BCD(With maximum output), Logic
- Job Description：
- Develop new platforms
- Improve cross-process issues
- Analyze / Improve / Track / Prevent WAT abnormalities and low yields
- Monitor products on the production line
- Import new products
- Promote / Execute client’s projects
- Respond to client’s problems and handle client complaints
- Achievement / Contribution：
- Successfully improved more than 40 cases, including more than 20 serious cases
- HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
- Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
- Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
- Defined more than 60 best known methods(BKM) to strengthen the BCD process
- Investigated countless WAT SPC alarms
- Specialize in operating numerous equipment
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
- Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors
- Successfully improved more than 40 cases, including more than 20 serious cases
Micron - Senior Defect Engineer
Jan., 2016 - Dec., 2016 (1 Year)
- Product：SI(Silicon interposer)
- Job Description：
- Analyze / Improve / Track / Prevent abnormal defects
- Promote / Execute cross-department projects
- Cross-departmental cooperation to improve the defect level
- Establish defect specification / category
- Achievement / Contribution：
- Successfully resolved the wafer edge low yield issue affecting the entire factory
- Established the first defect specification / category in our department
- Expert in operating SEM, EDS, Leica
Master’s Experience
National Chiao Tung University - Electronics Engineering
National Central University - Chemical and Materials Engineering
Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou
GPA：3.8 / 4
Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation
Laboratory：National Applied Research Laboratories(NARLabs)
Achievement / Contribution：
- Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
- Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow
2012 - 2014
2012 - 2014
Skills
- Semiconductor Process
- Semiconductor Physics and Devices
- Semiconductor Materials
- Electrical Analysis
- Electrical Measurement (DC/TLP SOA)
- Yield Analysis
- Data Statistical Analysis
- Risk Assessment and Strategy Formulation
- BCD Process
- BCD Device Analysis
Tools
Excel PowerPoint Word
Language
- Chinese
- English - TOEIC：760
陳嘉豪
資深主任製程整合工程師
- 6年半導體製程經驗
- 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
- 掌管全廠最大量產品BCD
- 成功改善超過40餘起案件
- 完成2項公司A級專案
- 訂定超過60餘項最佳化條件(BKM)
- 熟悉多台機台操作
新竹縣竹北市
+886 0989-929-413
工作經歷
UMC 聯華電子 - 資深主任製程整合工程師
一月 2017 - Present (5年)
- 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
- 負責產品：BCD(全廠最大產量)、Logic
- 工作內容：
- 開發新平台(Platform)
- 改善跨製程問題
- WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
- 監控線上產品
- 導入新產品
- 客戶專案的推動 / 執行
- 回覆客戶問題及處理客訴
- 成就 / 貢獻：
- 成功改善40餘起案子，其中超過20項重大案件
- HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
- 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
- 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
- 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
- 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
- 熟悉多台機台操作
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
- 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定
- 成功改善40餘起案子，其中超過20項重大案件
碩士學歷
Micron 美光科技 - 高級缺陷改善工程師
一月 2016 - 十二月 2016 (1年)
- 負責產品：SI(Silicon interposer)
- 工作內容：
- 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
- 跨部門專案的推動 / 執行
- 跨部門合作改善缺陷數量
- 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 成就 / 貢獻：
- 成功解決影響全廠的Wafer edge low yield issue
- 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 熟悉SEM, EDS, Leica機台操作
國立交通大學 - 電子工程學研究所
國立中央大學 - 化學工程與材料工程學研究所
指導教授：侯拓宏, 周正堂 教授
GPA：3.8/4
期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)
實驗地點：國家實驗研究院(NARLabs)
成就 / 貢獻：
- 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
- 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程
2012 - 2014
2012 - 2014
技能
- 半導體製程
- 半導體物理
- 半導體材料
- 電性分析
- 電性量測(DC/TLP SOA)
- 良率分析
- 資料統計分析
- 風險評估分析及應對策略擬定
- BCD 製程
- BCD 元件分析
擅長工具
Excel PowerPoint Word
語言
- 中文
- 英文 - TOEIC：760
Jia-Hao Chen
Senior Principal Process Integration Engineer(PIE)
- 6 years' experience in semiconductor field
- Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- In charge of the product BCD with maximum output in the whole factory
- Successfully improved more than 40 cases
- Finished 2 of our company's top projects
- Defined more than 60 best known methods(BKM)
- Specialize in operating numerous equipment
Hsinchu, Taiwan
+886 0989-929-413
Work Experience
UMC - Senior Principal Process Integration Engineer
Jan., 2017 - Present (5 Years)
- Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- Product：BCD(With maximum output), Logic
- Job Description：
- Develop new platforms
- Improve cross-process issues
- Analyze / Improve / Track / Prevent WAT abnormalities and low yields
- Monitor products on the production line
- Import new products
- Promote / Execute client’s projects
- Respond to client’s problems and handle client complaints
- Achievement / Contribution：
- Successfully improved more than 40 cases, including more than 20 serious cases
- HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
- Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
- Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
- Defined more than 60 best known methods(BKM) to strengthen the BCD process
- Investigated countless WAT SPC alarms
- Specialize in operating numerous equipment
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
- Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors
- Successfully improved more than 40 cases, including more than 20 serious cases
Micron - Senior Defect Engineer
Jan., 2016 - Dec., 2016 (1 Year)
- Product：SI(Silicon interposer)
- Job Description：
- Analyze / Improve / Track / Prevent abnormal defects
- Promote / Execute cross-department projects
- Cross-departmental cooperation to improve the defect level
- Establish defect specification / category
- Achievement / Contribution：
- Successfully resolved the wafer edge low yield issue affecting the entire factory
- Established the first defect specification / category in our department
- Expert in operating SEM, EDS, Leica
Master’s Experience
National Chiao Tung University - Electronics Engineering
National Central University - Chemical and Materials Engineering
Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou
GPA：3.8 / 4
Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation
Laboratory：National Applied Research Laboratories(NARLabs)
Achievement / Contribution：
- Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
- Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow
2012 - 2014
2012 - 2014
Skills
- Semiconductor Process
- Semiconductor Physics and Devices
- Semiconductor Materials
- Electrical Analysis
- Electrical Measurement (DC/TLP SOA)
- Yield Analysis
- Data Statistical Analysis
- Risk Assessment and Strategy Formulation
- BCD Process
- BCD Device Analysis
Tools
Excel PowerPoint Word
Language
- Chinese
- English - TOEIC：760