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Taiwan
台灣
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China University of Science and Technology
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AI工程師、機器學習工程師、深度學習工程師、資料科學家、Machine Learning Engineer、Deep Learning Engineer、Data Scientist
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ASML
ASML Taiwan 台灣艾司摩爾
Central Ammunition Depot, Ministry of Defense
Dialog Semiconductor 德商戴樂格半導體有限公司台灣分公司
Digi+ Program in NHRI (Genomics Analysis and Precision Medicine)
Explosive Ordnance Disposal
Industrial Technology Research Institute
Lextar隆達電子
Lexta隆達電子
Matsu Support Battalion, Ministry of Defense
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  • Exclude read results
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Avatar of the user.
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Available for paid companies
設備專案工程師 @日月光半導體製造股份有限公司 ADVANCED SEMICONDUCTOR ENGINEERING, INC.
・
2020 ~ Present
工程師
Within three months
Equipment repair and maintenance
Wire bonding process
Python
Employed
・
Open to opportunities
Full-time / Interested in working remotely
4-6 years
國立高雄科技大學 National Kaohsiung University of Science and Technology
・
電腦與通訊工程系
Avatar of Kuang huan Cheng.
Avatar of Kuang huan Cheng.
Kuang huan Cheng
Instructor @Digi+ Program in NHRI (Genomics Analysis and Precision Medicine)
・
2022 ~ Present
工程師
Within three months
the genetic variants in different population. Programming 1. R statistics, Shell, python languages. 2. Familiar with Linux system. Leadership 1. Lead company members to achieve the goals with honor. 2. Coordinate with other units to accomplish the missions. English 1. Toeic: 860 scoremonths training in US. Chemistry 1. Specialize in synthesis compounds. 2. Unexploded ordnance disposal. Work Experience Instructor in National Health Research Institutes (Digi+ talent Program), Julynow Guide interns to develop polygenic risk scores in breast cancer and hypertension. Precision health on
+leadership
+biomedical
R
Studying
Full-time / Interested in working remotely
6-10 years
National Chung Hsing University
・
Biomedical
Avatar of 陳嘉豪.
Offline
Avatar of 陳嘉豪.
Offline
陳嘉豪
資深產品工程師 @Dialog Semiconductor 德商戴樂格半導體有限公司台灣分公司
・
2022 ~ Present
工程師
Within one month
量測(DC/TLP SOA) 良率分析 資料統計分析 風險評估分析及應對策略擬定 BCD 製程 BCD 元件分析 擅長工具 Excel PowerPoint Word 語言 中文 英文 - TOEIC：760 Jia-Hao Chen Senior Principal Process Integration Engineer(PIE) 6 years' experience in semiconductor field Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc. In charge of the product BCD with maximum output in the whole factory Successfully improved more than
半導體製程相關
半導體物理
半導體材料
Employed
Full-time / Interested in working remotely
6-10 years
國立交通大學 National Chiao Tung University
・
電子工程
100+
Avatar of 李沛樺.
Avatar of 李沛樺.
李沛樺
工程師 @愛科國際管理顧問有限公司(RiskVal)
・
2016 ~ 2018
工程師
More than one year
維護供應商後台及排除供應商問題。 目前就職於台灣人壽。 工程師 城市，TW [email protected] Abilities 技能 Graphic 平面設計 Illustrator、Photoshop及Indesign Languages 語言 TOEIC 600 Programming 程式 Javascript、JQuery、CSS、HTML、Java、Spring Boot、Python、Tomcat、Linux、Shell Script、PL SQL、MS SQL、Git 經歷 2020 / 03 》台灣人壽 2018 / 08 ~ 2020 / 02 》電商MOMO - SCM 供應商後台維護 商品
illustrator
toeic
powerpoint
Full-time / Interested in working remotely
4-6 years
中國科技大學
・
視覺傳達設計系
Avatar of 楊沛中.
Avatar of 楊沛中.
楊沛中
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HVM TS Production Engineer Mechatronics @ASML
・
2021 ~ Present
工程師
Within three months
Pro/E、Inventor 工具軟體：Word、Excel、PowerPoint、Outlook 專業知識 自動化技術 機電整合 製程改善/優化 PLC、機械手臂 光學原理 Language 中文(流利) 英文(基本) Toeic 650 持續精進中 作品介紹： 性能檢查機 設備說明：產品組裝完後進行產品相關性能參數檢測。 開發特色： 1. 開發利用Load Cell
Word
PowerPoint
Excel
Employed
Full-time / Interested in working remotely
4-6 years
國立臺灣科技大學
・
自動化及控制研究所
Avatar of the user.
Avatar of the user.
Available for paid companies
技術員 @泰林科技
・
2009 ~ 2011
工程師
More than one year
ASP.NET
C#
JavaScript
Full-time / Not interested in working remotely
6-10 years
明新科技大學
・
雲端科技與商務應用
Avatar of Dean Huang.
Avatar of Dean Huang.
Dean Huang
產線輪班課長 @台星科股份有限公司
・
2022 ~ 2024
工程師
Within two months
make real. VBA tool maintaining and enhancing. Repair and maintain Probe Cards. Be in contact and have meeting with customers. Make sure delivery date of Probe Card is on time. Enhance/Overhauling PMS(Part Management system) functions. Design/Create Probe Card reports. Analyze Probe Card test data. 學歷國立虎尾科技大學 National Formosa University 飛機工程系 技能 Excel/Access JavaScript / ES6 / jQuery HTML/CSS SQL/Oracle PYTHON 語言 English — TOIEC/6) Japanese — N5
Excel
JavaScript / ES6 / jQuery
HTML/CSS
Employed
・
Open to opportunities
Full-time / Interested in working remotely
6-10 years
國立虎尾科技大學 National Formosa University
・
飛機工程系
Avatar of the user.
Avatar of the user.
Available for paid companies
Senior manager @Lexta隆達電子
・
2010 ~ Present
工程師
More than one year
AutoCAD
Excel
Full-time / Interested in working remotely
6-10 years
國立中正大學
・
物理, 光電, 雷射

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Within one month
Avatar of 陳嘉豪.
陳嘉豪
資深主任製程整合工程師
Dialog Semiconductor 德商戴樂格半導體有限公司台灣分公司
・
2022 ~ Present
台灣新竹
Professional Background
Current status
Employed
Job Search Progress
Professions
Process Engineer
Fields of Employment
Semiconductor
Work experience
6-10 years
Management
None
Skills
半導體製程相關
半導體物理
半導體材料
電性分析
良率分析
資料統計分析
風險評估分析及應對策略擬定
BCD Process
BCD Device Analysis
Excel
PowerPoint
Word
Languages
English
・
Professional
Job search preferences
Positions
工程師
Job types
Full-time
Locations
台灣新竹市
Remote
Interested in working remotely
Freelance
No
Educations
School
國立交通大學 National Chiao Tung University
Major
電子工程
Print

陳嘉豪

資深主任製程整合工程師

  • 6年半導體製程經驗
  • 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
  • 掌管全廠最大量產品BCD
  • 成功改善超過40餘起案件
  • 完成2項公司A級專案
  • 訂定超過60餘項最佳化條件(BKM)
  • 熟悉多台機台操作

  新竹縣竹北市

  [email protected]

  +886 0989-929-413

工作經歷


UMC 聯華電子 - 資深主任製程整合工程師

一月 2017 - Present (5年)

  • 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
  • 負責產品：BCD(全廠最大產量)、Logic
  • 工作內容：
    • 開發新平台(Platform)
    • 改善跨製程問題
    • WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
    • 監控線上產品
    • 導入新產品
    • 客戶專案的推動 / 執行
    • 回覆客戶問題及處理客訴
  • 成就 / 貢獻：
    • 成功改善40餘起案子，其中超過20項重大案件
      • HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
    • 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
    • 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
    • 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
    • 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
    • 熟悉多台機台操作
      • Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
    • 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定








碩士學歷

Micron 美光科技 - 高級缺陷改善工程師

一月 2016 - 十二月 2016 (1年)

  • 負責產品：SI(Silicon interposer)
  • 工作內容：
    • 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
    • 跨部門專案的推動 / 執行
    • 跨部門合作改善缺陷數量
    • 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
  • 成就 / 貢獻：
    • 成功解決影響全廠的Wafer edge low yield issue
    • 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
    • 熟悉SEM, EDS, Leica機台操作

國立交通大學 - 電子工程學研究所

國立中央大學 - 化學工程與材料工程學研究所

  • 指導教授：侯拓宏, 周正堂 教授

  • GPA：3.8/4

  • 期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory

  • 論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)

  • 實驗地點：國家實驗研究院(NARLabs)

  • 成就 / 貢獻：

    • 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
    • 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程

2012 - 2014

2012 - 2014

技能

  • 半導體製程
  • 半導體物理
  • 半導體材料
  • 電性分析
  • 電性量測(DC/TLP SOA)
  • 良率分析
  • 資料統計分析
  • 風險評估分析及應對策略擬定
  • BCD 製程
  • BCD 元件分析

擅長工具

  Excel   PowerPoint   Word

語言

  • 中文
  • 英文 - TOEIC：760

Jia-Hao Chen

Senior Principal Process Integration Engineer(PIE)

  • 6 years' experience in semiconductor field
  • Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
  • In charge of the product BCD with maximum output in the whole factory
  • Successfully improved more than 40 cases
  • Finished 2 of our company's top projects
  • Defined more than 60 best known methods(BKM)
  • Specialize in operating numerous equipment

  Hsinchu, Taiwan

  [email protected]

  +886 0989-929-413

Work Experience

UMC - Senior Principal Process Integration Engineer

Jan., 2017 - Present (5 Years)

  • Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
  • Product：BCD(With maximum output), Logic
  • Job Description：
    • Develop new platforms
    • Improve cross-process issues
    • Analyze / Improve / Track / Prevent WAT abnormalities and low yields
    • Monitor products on the production line
    • Import new products
    • Promote / Execute client’s projects
    • Respond to client’s problems and handle client complaints
  • Achievement / Contribution：
    • Successfully improved more than 40 cases, including more than 20 serious cases
      • HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
    • Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
    • Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
    • Defined more than 60 best known methods(BKM) to strengthen the BCD process
    • Investigated countless WAT SPC alarms
    • Specialize in operating numerous equipment
      • Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
    • Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors





Micron - Senior Defect Engineer

Jan., 2016 - Dec., 2016 (1 Year)

  • Product：SI(Silicon interposer)
  • Job Description：
    • Analyze / Improve / Track / Prevent abnormal defects
    • Promote / Execute cross-department projects
    • Cross-departmental cooperation to improve the defect level
    • Establish defect specification / category
  • Achievement / Contribution：
    • Successfully resolved the wafer edge low yield issue affecting the entire factory
    • Established the first defect specification / category in our department
    • Expert in operating SEM, EDS, Leica

Master’s Experience


National Chiao Tung University - Electronics Engineering

National Central University - Chemical and Materials Engineering

  • Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou

  • GPA：3.8 / 4

  • Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory

  • Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation

  • Laboratory：National Applied Research Laboratories(NARLabs)　

  • Achievement / Contribution：

    • Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
    • Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow

2012 - 2014

2012 - 2014

Skills

  • Semiconductor Process
  • Semiconductor Physics and Devices
  • Semiconductor Materials
  • Electrical Analysis
  • Electrical  Measurement (DC/TLP SOA)
  • Yield Analysis
  • Data Statistical Analysis
  • Risk Assessment and Strategy Formulation
  • BCD Process
  • BCD Device Analysis

Tools

  Excel  PowerPoint  Word

Language

  • Chinese
  • English - TOEIC：760














Resume
Profile
Print

陳嘉豪

資深主任製程整合工程師

  • 6年半導體製程經驗
  • 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
  • 掌管全廠最大量產品BCD
  • 成功改善超過40餘起案件
  • 完成2項公司A級專案
  • 訂定超過60餘項最佳化條件(BKM)
  • 熟悉多台機台操作

  新竹縣竹北市

  [email protected]

  +886 0989-929-413

工作經歷


UMC 聯華電子 - 資深主任製程整合工程師

一月 2017 - Present (5年)

  • 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
  • 負責產品：BCD(全廠最大產量)、Logic
  • 工作內容：
    • 開發新平台(Platform)
    • 改善跨製程問題
    • WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
    • 監控線上產品
    • 導入新產品
    • 客戶專案的推動 / 執行
    • 回覆客戶問題及處理客訴
  • 成就 / 貢獻：
    • 成功改善40餘起案子，其中超過20項重大案件
      • HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
    • 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
    • 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
    • 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
    • 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
    • 熟悉多台機台操作
      • Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
    • 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定








碩士學歷

Micron 美光科技 - 高級缺陷改善工程師

一月 2016 - 十二月 2016 (1年)

  • 負責產品：SI(Silicon interposer)
  • 工作內容：
    • 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
    • 跨部門專案的推動 / 執行
    • 跨部門合作改善缺陷數量
    • 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
  • 成就 / 貢獻：
    • 成功解決影響全廠的Wafer edge low yield issue
    • 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
    • 熟悉SEM, EDS, Leica機台操作

國立交通大學 - 電子工程學研究所

國立中央大學 - 化學工程與材料工程學研究所

  • 指導教授：侯拓宏, 周正堂 教授

  • GPA：3.8/4

  • 期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory

  • 論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)

  • 實驗地點：國家實驗研究院(NARLabs)

  • 成就 / 貢獻：

    • 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
    • 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程

2012 - 2014

2012 - 2014

技能

  • 半導體製程
  • 半導體物理
  • 半導體材料
  • 電性分析
  • 電性量測(DC/TLP SOA)
  • 良率分析
  • 資料統計分析
  • 風險評估分析及應對策略擬定
  • BCD 製程
  • BCD 元件分析

擅長工具

  Excel   PowerPoint   Word

語言

  • 中文
  • 英文 - TOEIC：760

Jia-Hao Chen

Senior Principal Process Integration Engineer(PIE)

  • 6 years' experience in semiconductor field
  • Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
  • In charge of the product BCD with maximum output in the whole factory
  • Successfully improved more than 40 cases
  • Finished 2 of our company's top projects
  • Defined more than 60 best known methods(BKM)
  • Specialize in operating numerous equipment

  Hsinchu, Taiwan

  [email protected]

  +886 0989-929-413

Work Experience

UMC - Senior Principal Process Integration Engineer

Jan., 2017 - Present (5 Years)

  • Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
  • Product：BCD(With maximum output), Logic
  • Job Description：
    • Develop new platforms
    • Improve cross-process issues
    • Analyze / Improve / Track / Prevent WAT abnormalities and low yields
    • Monitor products on the production line
    • Import new products
    • Promote / Execute client’s projects
    • Respond to client’s problems and handle client complaints
  • Achievement / Contribution：
    • Successfully improved more than 40 cases, including more than 20 serious cases
      • HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
    • Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
    • Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
    • Defined more than 60 best known methods(BKM) to strengthen the BCD process
    • Investigated countless WAT SPC alarms
    • Specialize in operating numerous equipment
      • Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
    • Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors





Micron - Senior Defect Engineer

Jan., 2016 - Dec., 2016 (1 Year)

  • Product：SI(Silicon interposer)
  • Job Description：
    • Analyze / Improve / Track / Prevent abnormal defects
    • Promote / Execute cross-department projects
    • Cross-departmental cooperation to improve the defect level
    • Establish defect specification / category
  • Achievement / Contribution：
    • Successfully resolved the wafer edge low yield issue affecting the entire factory
    • Established the first defect specification / category in our department
    • Expert in operating SEM, EDS, Leica

Master’s Experience


National Chiao Tung University - Electronics Engineering

National Central University - Chemical and Materials Engineering

  • Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou

  • GPA：3.8 / 4

  • Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory

  • Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation

  • Laboratory：National Applied Research Laboratories(NARLabs)　

  • Achievement / Contribution：

    • Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
    • Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow

2012 - 2014

2012 - 2014

Skills

  • Semiconductor Process
  • Semiconductor Physics and Devices
  • Semiconductor Materials
  • Electrical Analysis
  • Electrical  Measurement (DC/TLP SOA)
  • Yield Analysis
  • Data Statistical Analysis
  • Risk Assessment and Strategy Formulation
  • BCD Process
  • BCD Device Analysis

Tools

  Excel  PowerPoint  Word

Language

  • Chinese
  • English - TOEIC：760