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Definition of Reputation Credits
謝宗殷 (Azure)
R&D technical manager
Tainan City, Taiwan
Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616
Work experience
R&D technical manager • UMC
June 2014 - March 2022
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development
Process integration engineer • Taiwan Semiconductor Manufacturing Company(TSMC)
July 2010 - April 2014
Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development
Education
2006 - 2009
National Yang Ming Chiao Tung University
Electrical Engineering & IC design
2002 - 2006
Chang Gung University，CGU
Electrical Engineering Department
Personal advantage
- Strong learning ability
- Good at teamwork
- High problem solving ability
Skills
- Reliability improvement
- Defect reduction
- Process Integration
- Yield Enhancement
- Failure Analysis
Language
- English — Intermediate
Japanese — Elementary
謝宗殷 (Azure)
R&D technical manager
Tainan City, Taiwan
Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616
Work experience
R&D technical manager • UMC
June 2014 - March 2022
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development
Process integration engineer • Taiwan Semiconductor Manufacturing Company(TSMC)
July 2010 - April 2014
Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development
Education
2006 - 2009
National Yang Ming Chiao Tung University
Electrical Engineering & IC design
2002 - 2006
Chang Gung University，CGU
Electrical Engineering Department
Personal advantage
- Strong learning ability
- Good at teamwork
- High problem solving ability
Skills
- Reliability improvement
- Defect reduction
- Process Integration
- Yield Enhancement
- Failure Analysis
Language
- English — Intermediate
Japanese — Elementary