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4〜6年
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主任工程師 @Silicon Motion2020 ~ 現在
・
資深數位工程師
1ヶ月以内
FPGA issues JMicron, Digital Design Senior Engineer , Sep 2017 ~ Jul 2020 RTL Design and Verification with Verilog and SystemVerilog Build project database and environment with Python and Makefile Maintain and fix UHS-I Design Maintain and fix Unipro and MPHY Design Maintain and develop USB3 Gen1&2 Physical Layer(PCS) Design Provide FPGA Verification Database and relative tools Deal with customer issues Lyra semiconductor Inc. 芯籟半導體股份有限公司, Design Verification Engineer ,Jan 2017 ~ Sep 2017 Develop USBPD RTL Design & Verification Develop Samsung AFC, Huawei SCP & QC3.0 Controller RTL Design
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6〜10年
逢甲大學
・
電子工程
工程師 @Andes Technology 晶心科技2022 ~ 現在
・
PM/產品經理/專案管理
6ヶ月以内
開發、維護，產品主要為PC端及FPGA的bridge，主要會在USB以及JTAG的韌體撰寫，主要負責為將code porting到不同的chip，目前還有負責公司CPU design的partition，將RTL code修改後透過eda tool做partition，主要的工作項目為這些。 軟體工程師 緯創軟體股份有限公司 五月五月 2022Taipei, Taiwan 駐點在聯
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4〜6年
逢甲大學
・
通訊工程
Full Stack Engineer, Web @MongoDB, Inc.2021 ~ 現在
・
Full Stack Engineer
1年以上
Buzzwords : - Front End: HTML, CSS, JavaScript, Typescript, React, Svelte, Styled-Components, Emotion, Theme-UI, SASS, Stylus, BEM, Storybook; - State Management: Context API, Redux, Redux-Saga; - Back End: GraphQL, Node, Express, - Databases: MongoDB, MySQL, Postgres, Oracle; - CMS: Contentful, Drupal, WordPress, Headless CMS (Gatsby, Next.js) ; - Unit and Automated Testing: Jest, RTL, Enzyme, Cucumber, Playwright; - Ecosystem: Design Systems, KISS, DRY; - Infrastructure: CI/CD (Drone, Buddy, Travis, GitLab CI) , AWS (EC2 , ECS, S3) , Docker, Kubernetes, Splunk. https://angeloreale.com Work Experience FebruaryPresent (1 year 4 months) Staff Full Stack Engineer, Web. MongoDB, Inc. Headquartered in
フルタイム / リモートワークのみ
4〜6年
Universidade Salvador
・
B.Tech. Degree in Systems Analysis and Development , Information Technology
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6〜10年
真理大學
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6〜10年
University of Colombo
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Bachelor of Computer Science6〜10年
國立清華大學
・
Computer Science
Hardware Engineer @Inspur Taiwan2019 ~ 現在
・
Hardware Engineer
1年以上
. Including motherboard bring up and system schematic design. Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving. Support 2U4N system with AMD platform. Including system card design and troubleshooting. 十二月七月 2021 Senior Hardware Engineer • Accton Developed Broadcom platform switch schematics design. Developed Broadcom high speed PHY module Developed CPU module for high speed switch with Intel Denverton platform. CPLD RTL coding is based on Altera CPLD. Measured high
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National Central University
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國立清華大學
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Computer Science
Meng-Shiun(Kobe) Yu
Email: Kobeyu.tw at gmail.com
I'm currently an NPU compiler engineer at Kneron, also a Ph.D. student at the department of computer science, National Tsing Hua University, Taiwan. My research interests include
compiler and runtime for deep learning accelerator; architecture/performance evaluations; compiler designs and optimizations.
Education
- Ph.D., Department of Computer Science, National Tsing Hua University 2017/9 ~ Present
- Advisor: Jenq-Kuen Lee
- M.A., Department of Electrical Engineering, National Chung Cheng University 2006/9 ~ 2008/10
- Advisor: Huei-Yung Lin
- Thesis: A Vision Surveillance System for Mobile Robot Using Omni-directional and PTZ Cameras
- B.A., Department of Electrical Engineering, National Chin Yi University of Technology 2004/9 ~ 2006/6
Work Experience
Kneron．NPU Compiler Engineer．2019 / 2 ~ Present
- Participated in the development of 6 NPU SoCs.
- Developed compiler to compress weights for NPU, metadata for firmware control flow.
- Propose a whole new NPU executable format(NEF) for the runtime.
- Developed binary utilities to merge/extract multiple models to/from single NEF file.
- Developed binary utilities to encrypt model file for KNEO AI app ( https://www.kneo.ai/ ).
- Developed just in time compiler for image accelerator, used in freeRTOS and Embedded Linux environment.
- Pre- and post-silicon verification(NPU and image accelerator).
- Debug mismatch between CSim and RTL or performance issue with firmware, CSim, and HW team.
- Survey advanced techniques, compiler: TVM, MLIR, runtime: TFRT, IREE, model/hardware co-design: network architecture search.
- Recruit and lead interns to complete specific research work.
Fongfu．Software Engineering Manager．2016 / 9 ~ 2018 / 6
- Build up a software team (~5 engineer) to deploy services on iOS/Android and Asus Zenbo.
- System architecture evaluation and planning (Mobile App, Web backend)
- Developed face recognition algorithm.
SmartAll．Senior Software Engineer．2016 / 2 ~ 2016 / 8
- Developed iOS App to control smart camera.
- Porting ffmpeg and face detection algorithm on iOS.
- Developed peer to peer commutation SDK.
MSI．Software Engineer．2013 / 11 ~ 2016 / 2
- Developed iOS App to control smart camera.
CEO(Create Electronic Optical Co., Ltd)．Software Engineer．2010 /1 ~ 2013/3
- Developed lane departure and forward collision warning systems using computer vision algorithms.
- Developed media player for driver recorder.
Skills
- Programming Language
- C/C++, Python and Shell script
- Compiler
- Construction and optimization
- Deep Learning
- Optimize and deploy neural network model to edge devices.
Publications
- The Support of MLIR HLS Adaptor for LLVM IR, Geng-Ming Liang, Chuan-Yue Yuan, Meng-Shiun Yu, Tai-Liang Chen, Kuan-Hsun Chen, and Jenq-Kuen Lee, ICPP EMS 2022, Bordeaux, France, Aug. 29 - Sep. 1, 2022. (Virtual).
- C++OpenCL4TVM: Support C++OpenCL Kernel for TVM NN Operators, Po-Yao Chang, Tai-Liang Chen, Yu-Tse Huang, Meng-Shiun Yu, Jenq-Kuen Lee, IWOCL 2022 (poster paper), 2022.
- Optimization with TVM Hybrid OP on RISC-V with P Extension, Chuan-Yue Yuan, Meng-Shiun Yu, Chao-Lin Lee, Chun-Chieh Yang, and Jenq-Kuen Lee, TVMcon 2021, Seattle, Dec. 15-17, 2021
- Support NNEF Execution Model for NNAPI, Yuan-Ming Chang, Chia-Yu Sung, Yu-Chien Sheu, Meng-Shiun Yu, Min-Yih Hsu, and Jenq-Kuen Lee, Journal of Supercomputing, 77, 10065-10096, Springer, 2021.
- NNBlocks: A Blockly Framework for AI Computing, Tai-Liang Chen, Yi-Ru Chen, Meng-Shiun Yu, and Jenq-Kuen Lee, Journal of Supercomputing, 77, 8622-8652, Springer, 2021
- Accelerating NNEF framework on OpenCL devices using clDNN, Meng-Shiun Yu, Tai-Liang Chen and Jenq-Kuen Lee, IWOCL 2020, Germany, May 2020 (poster paper).
- A Robot Vision System for Visual Surveillance, M. S. Yu, H. Wu, H. Y. Lin, International Journal of Innovative Computing, Information and Control, Vol. 10, No. 4, pp. 1267-1274, Aug. 2014.
- Lane departure and front collision warning using a single camera, H. Y. Lin, L. Q. Chen, M. S. Yu, International Symposium on Intelligent Signal Processing and Communication System, pp. 64-69, Nov. 2012.
Talks
Neural Network File Format for Inference Framework．COSCUP．2020/08/02
機器學習應用於蔬果辨識．台灣人工智慧學校 台中分校．2018/11/28
社群與企業之開源專案合作經驗分享：以阿龜微氣候天眼通為例 ．g0v summit．2018/10/6
Agrino應用於農業感測的開源專案．COSCUP．2018/8/11
那些夜裡用啤酒打造的田間感測器．COSCUP．2017/8/6
Meng-Shiun(Kobe) Yu
Email: Kobeyu.tw at gmail.com
I'm currently an NPU compiler engineer at Kneron, also a Ph.D. student at the department of computer science, National Tsing Hua University, Taiwan. My research interests include
compiler and runtime for deep learning accelerator; architecture/performance evaluations; compiler designs and optimizations.
Education
- Ph.D., Department of Computer Science, National Tsing Hua University 2017/9 ~ Present
- Advisor: Jenq-Kuen Lee
- M.A., Department of Electrical Engineering, National Chung Cheng University 2006/9 ~ 2008/10
- Advisor: Huei-Yung Lin
- Thesis: A Vision Surveillance System for Mobile Robot Using Omni-directional and PTZ Cameras
- B.A., Department of Electrical Engineering, National Chin Yi University of Technology 2004/9 ~ 2006/6
Work Experience
Kneron．NPU Compiler Engineer．2019 / 2 ~ Present
- Participated in the development of 6 NPU SoCs.
- Developed compiler to compress weights for NPU, metadata for firmware control flow.
- Propose a whole new NPU executable format(NEF) for the runtime.
- Developed binary utilities to merge/extract multiple models to/from single NEF file.
- Developed binary utilities to encrypt model file for KNEO AI app ( https://www.kneo.ai/ ).
- Developed just in time compiler for image accelerator, used in freeRTOS and Embedded Linux environment.
- Pre- and post-silicon verification(NPU and image accelerator).
- Debug mismatch between CSim and RTL or performance issue with firmware, CSim, and HW team.
- Survey advanced techniques, compiler: TVM, MLIR, runtime: TFRT, IREE, model/hardware co-design: network architecture search.
- Recruit and lead interns to complete specific research work.
Fongfu．Software Engineering Manager．2016 / 9 ~ 2018 / 6
- Build up a software team (~5 engineer) to deploy services on iOS/Android and Asus Zenbo.
- System architecture evaluation and planning (Mobile App, Web backend)
- Developed face recognition algorithm.
SmartAll．Senior Software Engineer．2016 / 2 ~ 2016 / 8
- Developed iOS App to control smart camera.
- Porting ffmpeg and face detection algorithm on iOS.
- Developed peer to peer commutation SDK.
MSI．Software Engineer．2013 / 11 ~ 2016 / 2
- Developed iOS App to control smart camera.
CEO(Create Electronic Optical Co., Ltd)．Software Engineer．2010 /1 ~ 2013/3
- Developed lane departure and forward collision warning systems using computer vision algorithms.
- Developed media player for driver recorder.
Skills
- Programming Language
- C/C++, Python and Shell script
- Compiler
- Construction and optimization
- Deep Learning
- Optimize and deploy neural network model to edge devices.
Publications
- The Support of MLIR HLS Adaptor for LLVM IR, Geng-Ming Liang, Chuan-Yue Yuan, Meng-Shiun Yu, Tai-Liang Chen, Kuan-Hsun Chen, and Jenq-Kuen Lee, ICPP EMS 2022, Bordeaux, France, Aug. 29 - Sep. 1, 2022. (Virtual).
- C++OpenCL4TVM: Support C++OpenCL Kernel for TVM NN Operators, Po-Yao Chang, Tai-Liang Chen, Yu-Tse Huang, Meng-Shiun Yu, Jenq-Kuen Lee, IWOCL 2022 (poster paper), 2022.
- Optimization with TVM Hybrid OP on RISC-V with P Extension, Chuan-Yue Yuan, Meng-Shiun Yu, Chao-Lin Lee, Chun-Chieh Yang, and Jenq-Kuen Lee, TVMcon 2021, Seattle, Dec. 15-17, 2021
- Support NNEF Execution Model for NNAPI, Yuan-Ming Chang, Chia-Yu Sung, Yu-Chien Sheu, Meng-Shiun Yu, Min-Yih Hsu, and Jenq-Kuen Lee, Journal of Supercomputing, 77, 10065-10096, Springer, 2021.
- NNBlocks: A Blockly Framework for AI Computing, Tai-Liang Chen, Yi-Ru Chen, Meng-Shiun Yu, and Jenq-Kuen Lee, Journal of Supercomputing, 77, 8622-8652, Springer, 2021
- Accelerating NNEF framework on OpenCL devices using clDNN, Meng-Shiun Yu, Tai-Liang Chen and Jenq-Kuen Lee, IWOCL 2020, Germany, May 2020 (poster paper).
- A Robot Vision System for Visual Surveillance, M. S. Yu, H. Wu, H. Y. Lin, International Journal of Innovative Computing, Information and Control, Vol. 10, No. 4, pp. 1267-1274, Aug. 2014.
- Lane departure and front collision warning using a single camera, H. Y. Lin, L. Q. Chen, M. S. Yu, International Symposium on Intelligent Signal Processing and Communication System, pp. 64-69, Nov. 2012.