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职场能力评价定义
KUO HUI LEE
I am a semiconductor engineer with 11 Years experiment in process handle, new product try run to mass product, TCAD simulation, WAT/CP Yield, Assembly.
New Taipei City, Taiwan Mail: 6[email protected]om.tw
Summary
- Experiment 6/8 inch wafers in TMBS SBR( Schottky Barrier ) / Power IC and Trench MOSFET component process and device develop.
- Experiment Silvaco. TCAD simulation in TMBS Schottky Diode new product develop.
- Knowledge assembly package flow
- Handle customize process / new device develop for back-end package / customization device require
Work Experience
1.June 2018 - Dec. 2020
Senior RD engineer
VISHAY GENERAL SEMICONDUCTOR
I join TMBS Schottky Diode team in Vishay Corp. It is 6 inch wafer foundry house and has assembly line. I implement process improvement and new product develop within difference package type.
Accomplishment
- Original recipe & process tuning and implement original product to have better electric performance.
- Developing new product experiment, device manufacture / package and pass difference process qualification like HTRB (High Temperature Reverse Bias) or HTGB (High Temperature Gate Bias).
- Developing new schottky barrier process, it has benefit at low cost and low thermal budge.
2. Aug. 2008 - June 2018
Principal process integration engineer
World Vanguard International Semiconductor Corporation
I join in World Vanguard International Semiconductor Corp. It is 8 inch wafer foundry house and I handle BCD is 40um process within 40V LDMOS & 5/3.3V NMOS & PMOS ,BJT,and 5V ,12V Zener Diode Device for tape out products.Trench MOSFET customer are the face in process and tuning production procedure to meet customer threshold voltage and leakage requirement.
Accomplishment
Power IC Accomplishments:
- Suggest new customer design DRC fail and implement to try run.
- Support customer request device and co-work with PDK team to verify by shuttle and define FMEA (Failure Mode & Effect Analysis) Document.
- Co-work Product team for mass products yield loss process improvement.
- Production in line SPC handle and improve with Photo,Thin film,Diffusion and Etch module
Trench MOSFET Accomplishments - Apply the polyimide and oxide / SiN passivation design guideline for customer different assembly type request
- Co-work with Product team for Low yield improvement and inform customer and the yield above 95%.
- Production in line SPC handle and improve with Photo,Thin film,Diffusion and Etch module
Education
Nation Cheng Kung University
Electrical Engineering • 2005 - 2007
I major in electronic material application in the semiconductor application. Master’s thesis used BaxSr1-xTiO3 within doping Mn element and then it was sputtered for MIS isolation layer by RF sputtering machine. discuss and manufacture by sputter within simple mask.
Skill
Language
- English
- Chinese
KUO HUI LEE
I am a semiconductor engineer with 11 Years experiment in process handle, new product try run to mass product, TCAD simulation, WAT/CP Yield, Assembly.
New Taipei City, Taiwan Mail: 6[email protected]om.tw
Summary
- Experiment 6/8 inch wafers in TMBS SBR( Schottky Barrier ) / Power IC and Trench MOSFET component process and device develop.
- Experiment Silvaco. TCAD simulation in TMBS Schottky Diode new product develop.
- Knowledge assembly package flow
- Handle customize process / new device develop for back-end package / customization device require
Work Experience
1.June 2018 - Dec. 2020
Senior RD engineer
VISHAY GENERAL SEMICONDUCTOR
I join TMBS Schottky Diode team in Vishay Corp. It is 6 inch wafer foundry house and has assembly line. I implement process improvement and new product develop within difference package type.
Accomplishment
- Original recipe & process tuning and implement original product to have better electric performance.
- Developing new product experiment, device manufacture / package and pass difference process qualification like HTRB (High Temperature Reverse Bias) or HTGB (High Temperature Gate Bias).
- Developing new schottky barrier process, it has benefit at low cost and low thermal budge.
2. Aug. 2008 - June 2018
Principal process integration engineer
World Vanguard International Semiconductor Corporation
I join in World Vanguard International Semiconductor Corp. It is 8 inch wafer foundry house and I handle BCD is 40um process within 40V LDMOS & 5/3.3V NMOS & PMOS ,BJT,and 5V ,12V Zener Diode Device for tape out products.Trench MOSFET customer are the face in process and tuning production procedure to meet customer threshold voltage and leakage requirement.
Accomplishment
Power IC Accomplishments:
- Suggest new customer design DRC fail and implement to try run.
- Support customer request device and co-work with PDK team to verify by shuttle and define FMEA (Failure Mode & Effect Analysis) Document.
- Co-work Product team for mass products yield loss process improvement.
- Production in line SPC handle and improve with Photo,Thin film,Diffusion and Etch module
Trench MOSFET Accomplishments - Apply the polyimide and oxide / SiN passivation design guideline for customer different assembly type request
- Co-work with Product team for Low yield improvement and inform customer and the yield above 95%.
- Production in line SPC handle and improve with Photo,Thin film,Diffusion and Etch module
Education
Nation Cheng Kung University
Electrical Engineering • 2005 - 2007
I major in electronic material application in the semiconductor application. Master’s thesis used BaxSr1-xTiO3 within doping Mn element and then it was sputtered for MIS isolation layer by RF sputtering machine. discuss and manufacture by sputter within simple mask.
Skill
Language
- English
- Chinese