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CakeResume Talent Search

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කොළඹ විශ්වවිද්‍යාලය, கொழும்பு பல்கலைகழகம்
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Accton
Andes Technology 晶心科技
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MongoDB, Inc.
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Avatar of 劉柏頡.
Avatar of 劉柏頡.
劉柏頡
主任工程師 @Silicon Motion
・
2020 ~ Present
資深數位工程師
Within one month
FPGA issues JMicron, Digital Design Senior Engineer , Sep 2017 ~ Jul 2020 RTL Design and Verification with Verilog and SystemVerilog Build project database and environment with Python and Makefile Maintain and fix UHS-I Design Maintain and fix Unipro and MPHY Design Maintain and develop USB3 Gen1&2 Physical Layer(PCS) Design Provide FPGA Verification Database and relative tools Deal with customer issues Lyra semiconductor Inc. 芯籟半導體股份有限公司, Design Verification Engineer ,Jan 2017 ~ Sep 2017 Develop USBPD RTL Design & Verification Develop Samsung AFC, Huawei SCP & QC3.0 Controller RTL Design
SystemVerilog
Xilinx FPGA
Debugging
Employed
・
Ready to interview
Full-time / Interested in working remotely
6-10 years
逢甲大學
・
電子工程
Avatar of 李冠緯.
Avatar of 李冠緯.
李冠緯
工程師 @Andes Technology 晶心科技
・
2022 ~ Present
PM/產品經理/專案管理
Within six months
開發、維護，產品主要為PC端及FPGA的bridge，主要會在USB以及JTAG的韌體撰寫，主要負責為將code porting到不同的chip，目前還有負責公司CPU design的partition，將RTL code修改後透過eda tool做partition，主要的工作項目為這些。 軟體工程師 緯創軟體股份有限公司 五月五月 2022Taipei, Taiwan 駐點在聯
Java
PPT
Excel
Employed
Full-time / Interested in working remotely
4-6 years
逢甲大學
・
通訊工程
Avatar of Angelo Reale.
Avatar of Angelo Reale.
Angelo Reale
Full Stack Engineer, Web @MongoDB, Inc.
・
2021 ~ Present
Full Stack Engineer
More than one year
Buzzwords : - Front End: HTML, CSS, JavaScript, Typescript, React, Svelte, Styled-Components, Emotion, Theme-UI, SASS, Stylus, BEM, Storybook; - State Management: Context API, Redux, Redux-Saga; - Back End: GraphQL, Node, Express, - Databases: MongoDB, MySQL, Postgres, Oracle; - CMS: Contentful, Drupal, WordPress, Headless CMS (Gatsby, Next.js) ; - Unit and Automated Testing: Jest, RTL, Enzyme, Cucumber, Playwright; - Ecosystem: Design Systems, KISS, DRY; - Infrastructure: CI/CD (Drone, Buddy, Travis, GitLab CI) , AWS (EC2 , ECS, S3) , Docker, Kubernetes, Splunk. https://angeloreale.com Work Experience FebruaryPresent (1 year 4 months) Staff Full Stack Engineer, Web. MongoDB, Inc. Headquartered in
Comprehensive
Get Things Done
Learning
Full-time / Remote Only
4-6 years
Universidade Salvador
・
B.Tech. Degree in Systems Analysis and Development , Information Technology
Avatar of the user.
Avatar of the user.
Available for paid companies
Android Lead @Downapp
・
2020 ~ Present
Senior Android Developer
Within one month
Android
Kotlin
Android SDK
Employed
Full-time / Interested in working remotely
6-10 years
真理大學
・
資訊工程
Avatar of the user.
Avatar of the user.
Available for paid companies
Senior Technical Lead @Pearson
・
2023 ~ Present
Senior Software Engineer
Within one month
Agile Software Development
Component Development
Requirement Gathering
Employed
・
Open to opportunities
Full-time / Interested in working remotely
6-10 years
University of Colombo
・
Bachelor of Computer Science
Avatar of the user.
Avatar of the user.
Available for paid companies
Ph.D. Student @NTHU
Software engineer
Within six months
C/C++
Python
Deep Learning
6-10 years
國立清華大學
・
Computer Science
Avatar of Min-Yung Wang (Martin).
Offline
Avatar of Min-Yung Wang (Martin).
Offline
Min-Yung Wang (Martin)
Hardware Engineer @Inspur Taiwan
・
2019 ~ Present
Hardware Engineer
More than one year
. Including motherboard bring up and system schematic design. Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving. Support 2U4N system with AMD platform. Including system card design and troubleshooting. 十二月七月 2021 Senior Hardware Engineer • Accton Developed Broadcom platform switch schematics design. Developed Broadcom high speed PHY module Developed CPU module for high speed switch with Intel Denverton platform. CPLD RTL coding is based on Altera CPLD. Measured high
Cadence OrCAD
Cadence Allegro
Cadence Concept HDL
Interested in working remotely
4-6 years
National Central University
・
Master of Physics
100+

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Definition of Reputation Credits

Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
Communication
Ability to convey information effectively and is willing to give and receive feedback.
Time Management
Ability to prioritize tasks based on importance; and have them completed within the assigned timeline.
Teamwork
Ability to work cooperatively, communicate effectively, and anticipate each other's demands, resulting in coordinated collective action.
Leadership
Ability to coach, guide, and inspire a team to achieve a shared goal or outcome effectively.
More than one year
Avatar of Min-Yung Wang (Martin).
Min-Yung Wang (Martin)
Hardware Engineer
Inspur Taiwan
・
2019 ~ Present
Taiwan
Professional Background
Current status
Job Search Progress
Professions
Hardware Engineer
Fields of Employment
Hardware
Work experience
4-6 years
Management
None
Skills
Cadence OrCAD
Cadence Allegro
Cadence Concept HDL
Word、PowerPoint、Excel、Outlook
Hardware Troubleshooting
Hardware Development
Verilog RTL coding base on Intel Altera CPLD
Python coding for BOM check
Languages
English
・
Fluent
Job search preferences
Positions
Hardware Engineer
Job types
Locations
Remote
Interested in working remotely
Freelance
No
Educations
School
National Central University
Major
Master of Physics
Print

Min-Yung Wang (Martin)

Hardware Engineer

An experienced electrical engineer of 5 + years specialized in x86 architecture circuit design and server system integration. Familiar high speed interface design and PCB layout review. Skilled at coordinating cross-function teams to make the design process more efficient and smooth.

 Taiwan

 

Work Experience 

Hardware Engineer  •  Inspur Taiwan

Developed lntel Whitely platform for 2U general server. Including system card design and system level design from EVT to MP.
Design the Open19 server system with AMD platform. Including motherboard bring up and system schematic design.
Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving.
Support 2U4N system with AMD platform. Including system card design and troubleshooting.

十二月 2019 - 七月 2021

Senior Hardware Engineer  •  Accton

Developed Broadcom platform switch schematics design.
Developed Broadcom high speed PHY module
Developed CPU module for high speed switch with Intel Denverton platform.
CPLD RTL coding is based on Altera CPLD.
Measured high speed Signal Integrity (CAUI4/CAUI/XFI/QSGMII/SGMII) .

五月 2019 - 十二月 2019

Senior Hardware Engineer  •  ASRock Rack

Developed high-density 2U4N system and OCP system with lntel grantley and purley platform schematics design.
Build design module for a half-width motherboard.
Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting.
Developed 25/10GbE high speed Ethernet schematics and layout guide.
Have experience of the overarching ODM project.

九月 2015 - 五月 2019

Education

2013 - 2015

National Central University

Master of Physics

2009 - 2013

National Dong Hwa University

Bachelor of Physics

Skills

Language

  • Cadence OrCAD
  • Cadence Allegro
  • Cadence Concept HDL
  • Word、PowerPoint、Excel、Outlook
  • Hardware Troubleshooting
  • Hardware Development
  • Verilog RTL coding based on Intel Altera CPLD
  • Python coding for BOM check
  • English — Advanced
  • Mandarin — Native speaker
Resume
Profile
Print

Min-Yung Wang (Martin)

Hardware Engineer

An experienced electrical engineer of 5 + years specialized in x86 architecture circuit design and server system integration. Familiar high speed interface design and PCB layout review. Skilled at coordinating cross-function teams to make the design process more efficient and smooth.

 Taiwan

 

Work Experience 

Hardware Engineer  •  Inspur Taiwan

Developed lntel Whitely platform for 2U general server. Including system card design and system level design from EVT to MP.
Design the Open19 server system with AMD platform. Including motherboard bring up and system schematic design.
Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving.
Support 2U4N system with AMD platform. Including system card design and troubleshooting.

十二月 2019 - 七月 2021

Senior Hardware Engineer  •  Accton

Developed Broadcom platform switch schematics design.
Developed Broadcom high speed PHY module
Developed CPU module for high speed switch with Intel Denverton platform.
CPLD RTL coding is based on Altera CPLD.
Measured high speed Signal Integrity (CAUI4/CAUI/XFI/QSGMII/SGMII) .

五月 2019 - 十二月 2019

Senior Hardware Engineer  •  ASRock Rack

Developed high-density 2U4N system and OCP system with lntel grantley and purley platform schematics design.
Build design module for a half-width motherboard.
Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting.
Developed 25/10GbE high speed Ethernet schematics and layout guide.
Have experience of the overarching ODM project.

九月 2015 - 五月 2019

Education

2013 - 2015

National Central University

Master of Physics

2009 - 2013

National Dong Hwa University

Bachelor of Physics

Skills

Language

  • Cadence OrCAD
  • Cadence Allegro
  • Cadence Concept HDL
  • Word、PowerPoint、Excel、Outlook
  • Hardware Troubleshooting
  • Hardware Development
  • Verilog RTL coding based on Intel Altera CPLD
  • Python coding for BOM check
  • English — Advanced
  • Mandarin — Native speaker