CakeResume 找人才

進階搜尋
On
4 到 6 年
6 到 10 年
10 到 15 年
15 年以上
Avatar of Cheng Wei Lin.
軟體工程師/產品工程師
一年內
have afforded me an in-depth understanding of the industry, its unique challenges, and the critical elements required to deliver high-quality software solutions. Senior Software Engineer Hsinchu City, [email protected] Skills Languages Chinese: Native speaker English: Intermediate Spanish: Begineer Tools C# C++ Verilog HDL Matlab PHP & MySQL LabVIEW Interests Photography Reading Badminton Backpacking Mountaineering Marathon Work Experience Senior Software Engineer , JanPresent SYNTEC TECHNOLOGY CO. LTD. , Hsinchu, Taiwan Develop and maintain the product of Laser cutting machine and Press Break with C# and C++ Design and implement complex
english
c++ and c#
Lightroom
就職中
全職 / 暫不考慮遠端工作
6 到 10 年
台灣大學工程科學研究所
軟體工程師
Avatar of Min-Yung Wang (Martin).
離線
Avatar of Min-Yung Wang (Martin).
離線
Hardware Engineer @Inspur Taiwan
2019 ~ 現在
Hardware Engineer
超過一年
design. Build design module for a half-width motherboard. Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting . Developed 25/10GbE high speed Ethernet schematics and layout guide. Have experience of the overarching ODM project. 九月五月 2019 EducationNational Central University Master of PhysicsNational Dong Hwa University Bachelor of Physics Skills Language Cadence OrCAD Cadence Allegro Cadence Concept HDL Word、PowerPoint、Excel、Outlook Hardware Troubleshooting Hardware Development Verilog RTL coding based on Intel Altera CPLD Python coding for BOM check English — Advanced Mandarin — N ative speaker
Cadence OrCAD
Cadence Allegro
Cadence Concept HDL
對遠端工作有興趣
4 到 6 年
National Central University
Master of Physics

最輕量、快速的招募方案,數百家企業的選擇

搜尋履歷,主動聯繫求職者,提升招募效率。

  • 瀏覽所有搜尋結果
  • 每日可無限次數開啟陌生對話
  • 搜尋僅開放付費企業檢視的履歷
  • 檢視使用者信箱 & 電話
搜尋技巧
1
嘗試搜尋最精準的關鍵字組合
資深 後端 php laravel
如果結果不夠多,再逐一刪除較不重要的關鍵字
2
將須完全符合的字詞放在雙引號中
"社群行銷"
3
在不想搜尋到的字詞前面加上減號,如果想濾掉中文字,需搭配雙引號使用 (-"人資")
UI designer -UX
免費方案僅能搜尋公開履歷。
升級至進階方案,即可瀏覽所有搜尋結果(包含數萬筆覽僅在 CakeResume 平台上公開的履歷)。

職場能力評價定義

專業技能
該領域中具備哪些專業能力(例如熟悉 SEO 操作,且會使用相關工具)。
問題解決能力
能洞察、分析問題,並擬定方案有效解決問題。
變通能力
遇到突發事件能冷靜應對,並隨時調整專案、客戶、技術的相對優先序。
溝通能力
有效傳達個人想法,且願意傾聽他人意見並給予反饋。
時間管理能力
了解工作項目的優先順序,有效運用時間,準時完成工作內容。
團隊合作能力
具有向心力與團隊責任感,願意傾聽他人意見並主動溝通協調。
領導力
專注於團隊發展,有效引領團隊採取行動,達成共同目標。
超過一年
Hardware Engineer
Inspur Taiwan
2019 ~ 現在
Taiwan
專業背景
目前狀態
求職階段
專業
硬體工程師
產業
硬體
工作年資
4 到 6 年
管理經歷
技能
Cadence OrCAD
Cadence Allegro
Cadence Concept HDL
Word、PowerPoint、Excel、Outlook
Hardware Troubleshooting
Hardware Development
Verilog RTL coding base on Intel Altera CPLD
Python coding for BOM check
語言能力
English
進階
求職偏好
希望獲得的職位
Hardware Engineer
預期工作模式
期望的工作地點
遠端工作意願
對遠端工作有興趣
接案服務
學歷
學校
National Central University
主修科系
Master of Physics
列印

Min-Yung Wang (Martin)

Hardware Engineer

An experienced electrical engineer of 5 + years specialized in x86 architecture circuit design and server system integration. Familiar high speed interface design and PCB layout review. Skilled at coordinating cross-function teams to make the design process more efficient and smooth.

 Taiwan

 

Work Experience 

Hardware Engineer  •  Inspur Taiwan

Developed lntel Whitely platform for 2U general server. Including system card design and system level design from EVT to MP.
Design the Open19 server system with AMD platform. Including motherboard bring up and system schematic design.
Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving.
Support 2U4N system with AMD platform. Including system card design and troubleshooting.

十二月 2019 - 七月 2021

Senior Hardware Engineer  •  Accton

Developed Broadcom platform switch schematics design.
Developed Broadcom high speed PHY module
Developed CPU module for high speed switch with Intel Denverton platform.
CPLD RTL coding is based on Altera CPLD.
Measured high speed Signal Integrity (CAUI4/CAUI/XFI/QSGMII/SGMII) .

五月 2019 - 十二月 2019

Senior Hardware Engineer  •  ASRock Rack

Developed high-density 2U4N system and OCP system with lntel grantley and purley platform schematics design.
Build design module for a half-width motherboard.
Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting.
Developed 25/10GbE high speed Ethernet schematics and layout guide.
Have experience of the overarching ODM project.

九月 2015 - 五月 2019

Education

2013 - 2015

National Central University

Master of Physics

2009 - 2013

National Dong Hwa University

Bachelor of Physics

Skills

Language


  • Cadence OrCAD
  • Cadence Allegro
  • Cadence Concept HDL
  • Word、PowerPoint、Excel、Outlook
  • Hardware Troubleshooting
  • Hardware Development
  • Verilog RTL coding based on Intel Altera CPLD
  • Python coding for BOM check

  • English — Advanced
  • Mandarin — Native speaker
履歷
個人檔案

Min-Yung Wang (Martin)

Hardware Engineer

An experienced electrical engineer of 5 + years specialized in x86 architecture circuit design and server system integration. Familiar high speed interface design and PCB layout review. Skilled at coordinating cross-function teams to make the design process more efficient and smooth.

 Taiwan

 

Work Experience 

Hardware Engineer  •  Inspur Taiwan

Developed lntel Whitely platform for 2U general server. Including system card design and system level design from EVT to MP.
Design the Open19 server system with AMD platform. Including motherboard bring up and system schematic design.
Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving.
Support 2U4N system with AMD platform. Including system card design and troubleshooting.

十二月 2019 - 七月 2021

Senior Hardware Engineer  •  Accton

Developed Broadcom platform switch schematics design.
Developed Broadcom high speed PHY module
Developed CPU module for high speed switch with Intel Denverton platform.
CPLD RTL coding is based on Altera CPLD.
Measured high speed Signal Integrity (CAUI4/CAUI/XFI/QSGMII/SGMII) .

五月 2019 - 十二月 2019

Senior Hardware Engineer  •  ASRock Rack

Developed high-density 2U4N system and OCP system with lntel grantley and purley platform schematics design.
Build design module for a half-width motherboard.
Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting.
Developed 25/10GbE high speed Ethernet schematics and layout guide.
Have experience of the overarching ODM project.

九月 2015 - 五月 2019

Education

2013 - 2015

National Central University

Master of Physics

2009 - 2013

National Dong Hwa University

Bachelor of Physics

Skills

Language


  • Cadence OrCAD
  • Cadence Allegro
  • Cadence Concept HDL
  • Word、PowerPoint、Excel、Outlook
  • Hardware Troubleshooting
  • Hardware Development
  • Verilog RTL coding based on Intel Altera CPLD
  • Python coding for BOM check

  • English — Advanced
  • Mandarin — Native speaker