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4-6 years
6-10 years
10-15 years
More than 15 years
Past
R&D process integration engineer @ UMC2014 ~ 2022
・
Semiconductor Engineer
More than one year
謝宗殷 (Azure) R&D technical manager Tainan City, Taiwan Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University. As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience. Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement. Email : [email protected] Phone:Work experience R&D technical manager • UMC JuneMarchnm FiNFET BEoL process development, product yield improvement and
Unemployed
・
Not open to opportunities
Full-time / Interested in working remotely
10-15 years
National Yang Ming Chiao Tung University
・
Electrical Engineering & IC design
Past
製程工程師 @台灣積體電路公司2018 ~ 2020
・
研發工程師
Within six months
setup 3. cost reduction 80w/month 4. slot effect improve 50% 5. defect improvement from 5 to 3 count/ wafer 台灣積體電路公司, 製程工程師process engineer, Jun 2018 ~ SepF18 N5 FEOL new tech transition 2. FINFET CD / depth SPC maintain 3. WPH improvement 50% 4.new tool import for production line expansion 5. DOE design uniformity improve 30% 6. Auto system coordinator and APC setup Equipment Process: TEL SCCM/VIGUS/F1000 Hitachi 9012 Measurement: (CDSEM/ SCD/
Unemployed
Full-time / Interested in working remotely
4-6 years
成功大學
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Definition of Reputation Credits
Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
Communication
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Time Management
Ability to prioritize tasks based on importance; and have them completed within the assigned timeline.
Teamwork
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Leadership
Ability to coach, guide, and inspire a team to achieve a shared goal or outcome effectively.
More than one year
United Senior process Integration engineer
UMC, United Microelectronics Company
・
2015 ~ Present
Professional Background
Current status
Job Search Progress
Professions
Other
Fields of Employment
Manufacturing
Work experience
2-4 years
Management
Skills
Languages
Job search preferences
Positions
Staff engineer
Job types
Full-time
Locations
Remote
Interested in working remotely
Freelance
Educations
School
National Taiwan University
Major
Master Degree of Chemical Engineering
Jing Yi Lin
R&D staff process integration engineer of 14 nm FinFET devices, team player and specialized in process flow design. Strong understanding of devices (FinFET, power MOSFET). Capable of executing new packages to enhance electrical performance and yield. Experienced in data extraction, analysis, and DOEs. Familiar with layout (GDS) , mask (JDV) systems, and a programmer of Fortran and python.
Work Experience
UMC, United Microelectronics Company
Staff Process Integration Engineer, Jul. 2019 - Now
- FinFET SRAM platform FEoL development and yield excellence
Senior Process Integration Engineer, Oct 2015 - Jun 2019
- 14 nm FinFET platform circuit layout and process flow design
- Defined UMC's first 14 nm product logic chip process corners with work function metal
- 3D silicon channel strain analysis and mobility boost by S/D Epi. processes
- High-k metal gate dimensions design for power consumption reduction
- MOL interconnect robustness, 14 nm FinFET yield peak 100%
Education
NTU, National Taiwan University
Master of Chemical Engineering, 2013 - 2015
- Silicon sheet electric zone melting thermal and crystallization simulation by phase field model, with finite element method and adaptive mesh by Fortran.
- Poster exhibition at CSSC-8 (international workshop on crystalline silicon for solar cells) in Bamberg, Germany
NTHU, National Tsing Hua University
Bachelor of Chemistry and Chemical Engineering, 2009 - 2013
- Interdisciplinary degree of chemical engineering and chemistry
Skills
English
- TOEFL 96
- TOEIC 945
Chinese (Native)
Software/Programming
- Microsoft suite
- AutoCAD/Inventor
- Fortran
- Python
Other skills
- MOSFET/FinFET
- SPC
- GDS
- JDV
Jing Yi Lin
R&D staff process integration engineer of 14 nm FinFET devices, team player and specialized in process flow design. Strong understanding of devices (FinFET, power MOSFET). Capable of executing new packages to enhance electrical performance and yield. Experienced in data extraction, analysis, and DOEs. Familiar with layout (GDS) , mask (JDV) systems, and a programmer of Fortran and python.
Work Experience
UMC, United Microelectronics Company
Staff Process Integration Engineer, Jul. 2019 - Now
- FinFET SRAM platform FEoL development and yield excellence
Senior Process Integration Engineer, Oct 2015 - Jun 2019
- 14 nm FinFET platform circuit layout and process flow design
- Defined UMC's first 14 nm product logic chip process corners with work function metal
- 3D silicon channel strain analysis and mobility boost by S/D Epi. processes
- High-k metal gate dimensions design for power consumption reduction
- MOL interconnect robustness, 14 nm FinFET yield peak 100%
Education
NTU, National Taiwan University
Master of Chemical Engineering, 2013 - 2015
- Silicon sheet electric zone melting thermal and crystallization simulation by phase field model, with finite element method and adaptive mesh by Fortran.
- Poster exhibition at CSSC-8 (international workshop on crystalline silicon for solar cells) in Bamberg, Germany
NTHU, National Tsing Hua University
Bachelor of Chemistry and Chemical Engineering, 2009 - 2013
- Interdisciplinary degree of chemical engineering and chemistry
Skills
English
- TOEFL 96
- TOEIC 945
Chinese (Native)
Software/Programming
- Microsoft suite
- AutoCAD/Inventor
- Fortran
- Python
Other skills
- MOSFET/FinFET
- SPC
- GDS
- JDV