CakeResume Talent Search

劉柏頡 6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations. Familiar with Simulator(VCS/Xcelium) and FPGA Synthesis tools(SNPS Synplify & ProtoCompiler, Xilinx Vivado). Experienced in script languages, such as Makefile, TCL, Perl and Python. Experienced with EDA tools, such as SNPS SpyGlass and CDNS LEC. Experienced in building some automatic flows using Jenkins and Git. Supervisor Engineer 城市，[email protected] Skills Language SystemVerilog & Verilog C/C++ Python Makefile Perl TCL Tool Xilinx Vivado Synplify/ProtoCompiler Xcelium

the TCP module, improving packet processing efficiency by 30%. Redesign the logging mechanism, increasing the searching and logging efficiency by 90%. Software Engineer • Syntec ( Kernel Architecture Section ) Sep~ DecMaintaining a multi-threaded CNC controller system using C++. Maintaining FPGA communication modules with Xilinx ISE using Verilog. Being the section contact window, classifying reported bugs and providing consulting to other departments. Lead and build up the communication error diagnosis SOP, providing sufficient logging and diagnostics from FPGA and CNC controller without impacting system performance, decreases technical support travel by 50%. Optimizing the EtherCAT

Science,Machine Learning and Internet of Things. University of Massachusetts-Amherst Electrical/Software Engineer Iselin,NJ [email protected] Skills UI/UX  Interface Design Web Design Sketch Bot Development Software Languages Java C/C++ Python Javascript (Node.js, React.js) Verilog Data Science Numpy Scipy Pandas Matplotlib T ensor Flow Plotly SQL Computer Aid Engineering Schematic Design: AutoCAD,, PSpice/HSpice Simulation Tools: Matlab/Simulink,Cadence,Multisim PCB Design: Eagle, Altium Embedded System Design Hardware Programming: Altera QuartuModelsim,FPGA , MPLAB/JTAG Experience Experience 01, FebPresent Lorem ipsum dolor

用C/C++語言設計動作並燒錄到Arduino中，使其輸出訊號操控伺服馬達，達成半自動化的控制。 而全自動化的研究是運用Verilog寫入FPGA，由FPGA設計動作輸出訊號控制步進馬達，整合影像處理與機械手臂，達成全自動化的控制。在製作專題中遇到了程

范盛泓 CEO Taipei City, Taiwan 有5年程式開發經驗 熟悉OpenCV, Matlab, C++, C, Swift, Pspice, Assembly language, Cadence, Verilog 工作經歷 CEO/Co-Founder • YouLink Holdings Inc 六月Present In early 2020, selected for the NTU Innovation Accelerator program, garnered over a thousand sign-ups within two weeks of launch on the university campus. Presently, the user base spans various national universities, with user accumulation rates surpassing those of the past Dcard. YouLink is dedicated to creating a social platform that bridges the

Engineering and Engineering Management Skills Programming Language Backend: Solid knowledge of backend programming, such as Golang, Python. Capability of reading and debugging with Java JDK8. Frontend: HTML/CSS/Javascript DevOps: Linux ShellScript, Selenium, Ansible ERP: SAP ABAP R/3, Fiori Numerical Analysis: MATLAB Hardware Programming: Verilog Applications & Software Familiar with RESTful APIs development using Golang. Hands on Container solutions. (Docker, Kubernetes) General Knowledge of MySQL, and other common databases with database design knowledge and proficiency in SQL language. Hands on Linux network utils such as iptables, ip/ifconfig Involved in Scrum

Cheng Wei Lin I am an experienced senior software engineer with a solid background in the numerical control industry, accumulating 8 years of hands-on experience. Throughout my career, I have excelled in collaborating with research and development teams, product teams, and software quality assurance teams. My expertise extends to languages such as C#, C++, and Verilog. I have made significant contributions to various projects within the domains of pressbrake, laser cutting, and laser welding. Notably, I have successfully completed projects such as the development of Computer-Aided Manufacturing software for pressbrake, motion