劉柏頡 6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations. Familiar with Simulator(VCS/Xcelium) and FPGA Synthesis tools(SNPS Synplify & ProtoCompiler, Xilinx Vivado). Experienced in script languages, such as Makefile, TCL, Perl and Python. Experienced with EDA tools, such as SNPS SpyGlass and CDNS LEC. Experienced in building some automatic flows using Jenkins and Git. Supervisor Engineer 城市,[email protected] Skills Language SystemVerilog & Verilog C/C++ Python Makefile Perl TCL Tool Xilinx Vivado Synplify/ProtoCompiler Xcelium
SystemVerilog
Xilinx FPGA
Debugging
Sudah bekerja
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Siap untuk wawancara
Full-time / Tertarik bekerja jarak jauh
6-10 tahun
逢甲大學
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電子工程
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