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FPGA issues JMicron, Digital Design Senior Engineer , Sep 2017 ~ Jul 2020 RTL Design and Verification with Verilog and SystemVerilog Build project database and environment with Python and Makefile Maintain and fix UHS-I Design Maintain and fix Unipro and MPHY Design Maintain and develop USB3 Gen1&2 Physical Layer(PCS) Design Provide FPGA Verification Database and relative tools Deal with customer issues Lyra semiconductor Inc. 芯籟半導體股份有限公司, Design Verification Engineer ,Jan 2017 ~ Sep 2017 Develop USBPD RTL Design & Verification Develop Samsung AFC, Huawei SCP & QC3.0 Controller RTL Design

開發、維護，產品主要為PC端及FPGA的bridge，主要會在USB以及JTAG的韌體撰寫，主要負責為將code porting到不同的chip，目前還有負責公司CPU design的partition，將RTL code修改後透過eda tool做partition，主要的工作項目為這些。 軟體工程師 緯創軟體股份有限公司 五月五月 2022Taipei, Taiwan 駐點在聯

Buzzwords : - Front End: HTML, CSS, JavaScript, Typescript, React, Svelte, Styled-Components, Emotion, Theme-UI, SASS, Stylus, BEM, Storybook; - State Management: Context API, Redux, Redux-Saga; - Back End: GraphQL, Node, Express, - Databases: MongoDB, MySQL, Postgres, Oracle; - CMS: Contentful, Drupal, WordPress, Headless CMS (Gatsby, Next.js) ; - Unit and Automated Testing: Jest, RTL, Enzyme, Cucumber, Playwright; - Ecosystem: Design Systems, KISS, DRY; - Infrastructure: CI/CD (Drone, Buddy, Travis, GitLab CI) , AWS (EC2 , ECS, S3) , Docker, Kubernetes, Splunk. https://angeloreale.com Work Experience FebruaryPresent (1 year 4 months) Staff Full Stack Engineer, Web. MongoDB, Inc. Headquartered in

. Including motherboard bring up and system schematic design. Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving. Support 2U4N system with AMD platform. Including system card design and troubleshooting. 十二月七月 2021 Senior Hardware Engineer • Accton Developed Broadcom platform switch schematics design. Developed Broadcom high speed PHY module Developed CPU module for high speed switch with Intel Denverton platform. CPLD RTL coding is based on Altera CPLD. Measured high