(1) Verification Planning
1.1 DSP platform module and/or system design
1.2 5G/6G modem module and/or system design
(2) Testbench Build-Up
1.1 Constrained random verification by SystemVerilog/UVM usage
1.2 Reference modeling
1.3 Assertion check
1.4 Coverage closure
(3) Coordination with Algorithm/Digital design/Software teams

<Mandatory>
1. (EE or CS) MS degree or above
2. Digital design (RTL) or design verification experience
3. OOP programming language and data structure experience (ex: C++/Java/SystemVerilog, etc)
4. Problem solving and debugging skills

<Optional>
1. Good understanding of computer architecture (CPU or DSP)
2. Good understanding of modem or communication knowledge