System-Level-Cache Design Architect

In this role, you will be a member of the System-Level-Cache (SLC) design team, working with architecture, modeling, silicon, software and other design teams to develop competitive SLC design. We are looking for highly motivated, hands-on individuals who are passionate about memory performance improvement to benefit memory access behavior in sophisticated system.

Major Responsibilities

• Co-work with system architect to develop competitive memory system architecture
• Analyze/improve memory system performance including latency and efficiency
• Responsible for micro architecture planning and RTL design coding
• Integrate IP into project and meet schedule and P.P.A. requirement
• Co-work with DV team to well verify RTL design
• Support software team to resolve memory system related issue

• Good knowledge in computer architecture, microarchitecture, and performance
• 3+ years of relevant experience in digital design RTL coding and integration
• Familiarity with the architecture and the micro-architectures of recent ARM processor is a plus
• Familiarity with AMBA AXI, CHI and LPDDR4/5 interfaces/protocols is a plus
• Familiarity with cache design is a plus
• Good communicating, problem solving, root causing and debugging skills