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1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Experience with verification methodologies and languages such as UVM or SystemVerilog. Experience in verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems). Preferred qualifications: Master's degree or PhD in Electrical Engi

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or relat

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with physical design verification flows and methodology (e.g., DRC, LVS, PERC, ESD signoff, ERC, antenna, DFM) using industry standard signoff tools. Experience managing various physical verification check runsets. Preferred qualifications: Master's degree or PhD in Elec

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in functional verification, performance validation, developing test plans, and diagnostic codes of modern processors. Experience with processor microarchitecture. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or related field. Experi

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

Google welcomes people with disabilities. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Taipei, Taiwan . Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. Experience verifying digital logic at RTL using SystemVerilog for ASICs. Experience verifying digital systems using standard IP componen

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Experience with RTL, low power (UPF/CPF), gate level (GLS) and formal

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh

【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.