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Logo of WASAI Technology.
* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills
OpenCL
Verilog
VHDL
80K ~ 200K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of ASML Taiwan 台灣艾司摩爾.
Job Title [Taiwan Pipeline] D&E-Firmware Design Engineer (FPGA)-Tainan Degree: Master Work Experience: 2-3 years, 4-9 years Travel: 25% Remote Work: Partially Job Description: Introduction to the job Be a FPGA firmware design engineer and join the world’s most advanced electron beam defect inspection equipment development. Responsible for e-Beam inspection sustaining system improvement project, customer special request, and issue investigation. Firmware design support for new system and tool dev
Regular earnings reach NT$40,000
No requirement for relevant working experience
No management responsibility
Logo of 浦飛爾科技有限公司.
1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
780K ~ 2.34M TWD / year
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus
Digital IC Designer
IC design
Memory
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
Logo of Morgan Philips Group.
Job Responsibilities: Engage in RTL/Digital circuit design, synthesis, and simulation/verification. Conduct FPGA synthesis and verification processes. Manage chip integration, algorithm implementation, and interface design. Generate test patterns.
1M ~ 3M TWD / year
3 years of experience required
No management responsibility
Logo of 緯創資通股份有限公司.
1. FPGA Development for server or communication applications , including IC design , Verilog coding , Simulation , Timing closure , Debug and Project maintenance. 2. Validate and Debug FPGA on prototype hardware system. 3. Co-work with Hardware and Software engineers in development. 4. Design tools implementation
Electronics Industry
40K ~ 60K TWD / month
2 years of experience required
No management responsibility
Logo of 力旺電子 eMemory.
力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 密碼演算法開發 2. 數位電路設計 (RTL) 3. 數位電路驗證 (UVM) 4. FPGA建置整合及驗證 -------------------------------------------------------------------------- 1. Crypto algorithm development 2. RTL design 3. UVM verification 4. FPGA prototype & emulation
Linux
UNIX
40K+ TWD / month
3 years of experience required
No management responsibility
Logo of Ali Tech.
1.Front-End/Modem (Baseband) Architecture Design for WiFi6/BT/BLE systems; 2.Optimization of Frontend/Modem circuits and simulation/verifications; 3.Digital Circuit Design and Verification – RTL Coding/Synthesis/STA/…
C++
FPGA
ASIC
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of 創未來科技有限公司.
##Job Description: ­- Develop host side firmware/software to cooperate with purpose-built FPGA IPs on Xilinx Zynq SoC or pure FPGA w/ softcore(s) ­- Help build the embedded Linux system (Petalinux) ­- Discuss with DSP team and digital design team and help to interface their needs ­- Develop and/or integrate Linux drivers. ##Skill: Familiar with: - C / C++, Python programming (user space) ­- Git version control ­- Petalinux / Yocto build tool
FPGA
Embedded Linux
Xilinx Zynq
60K ~ 100K TWD / month
No management responsibility
Logo of Ali Tech.
1.高速介面(SerDes)類比電路設計 2.Circuit design of CTLE/CDR/DFE/PLL/TX 3.Familiar with SerDes and DDR PHY architecture (ex: PCIe3 / USB3 / HDMI2 / DDR4 / LPDDR4/4x ...etc)
C++
FPGA
PLL
1.8M ~ 2.3M TWD / year
No management responsibility

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