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SUMMARY The Application Engineer is responsible for providing world-class assistance to customers in the usage of RedHawk/RedHawk-SC, as well as for leveraging knowledge and relationships to assist in growing our software business in line with the corporate vision and performance expectations. Apply knowledge and experience in the areas of RTL design, custom circuit analysis, high-speed VLSI design, standard cell physical layout, power-grid extraction, timing analysis, noise analysis, and voltag

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Experience with RTL, low power (UPF/CPF), gate level (GLS) and formal

Tensorcom, a pioneer in developing innovative semiconductors for high-speed millimeter wave, ultra-low power, wireless communication chipsets, is looking for a candidate who is interested in working on complex, low power, ASIC designs for our next generation WiGig/IEEE 802.11ad compliant SoCs. The interested candidate will participate in a range of ASIC development activities such as defining the SoC architecture, the development of RTL code, the taping-out of the chip, and the evaluation of

Tensorcom, a pioneer in developing innovative semiconductors for high-speed millimeter wave, ultra-low power, wireless communication chipsets, is looking for a candidate who is interested in working on complex ASIC designs for our next generation 60GHz, IEEE 802.11ad/WiGig compliant SoCs with specific emphasis on developing RTL code for the digital baseband module. The candidate will participate in a range of ASIC development activities such as defining the digital modem architecture, the evalua

1. Verify RTL design with System Verilog and UVM verification methodology. 2. PCIe or USB or SATA related VIP test maintenance and development. 3. Develop verification platform or behavioral models. 4.Test planning, testbench documentation and development.