CakeResume Job Search

Google welcomes people with disabilities. Minimum qualifications: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of of experience in high-performance CPU or AI accelerator logic/RTL design including microarchitecture definition and Power Performance Area optimizations. Experience with CPU or AI accelerator integration with SOC. Preferred qualifications: PhD in Electrical Engineering or Computer S

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with microprocessor architecture. Experience with logic synthesis techniques to optimize RTL code, performance, power, and design techniques. Preferred qual

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Experience with microprocessor architecture. Experience with logic design. Preferred qualifications: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. Experience with modern processor microarchitecture and related technologies

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Experience with CPU or AI accelerator

Maintain and integrate PCIe/ USB3.2/USB4/ related IP and peripheral design. Verify PCIe/ USB3.2/USB4 related IP.

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh

Maintain and integrate PCIe/ USB3.2/USB4/ related IP and peripheral design. Verify PCIe/ USB3.2/USB4 related IP.

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with microprocessor architecture. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science. Experience with modern pro

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Academic coursework in Computer Architecture or Digital Designs. Experience with C/C++ or Verilog/SystemVerilog. Preferred qualifications: Master's degree or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field. 3 years of experience in RTL design or verif

1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus