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studio with a vision to create innovative and engaging games for a global audience. We are looking for a talented and imaginative Level Designer to join our team and help us build immersive and unforgettable worlds. About the role: As a Level Designer, you will be responsible for crafting the very spaces where players will experience our games. You will: Design engaging and challenging levels that fit seamlessly with the overall game design. Create compelling n

Product platform HW system design integration Schematic design, PCB layout design and review RFQ/PRD research and feedback Component survey and technology study BOM creation and maintenance Circuit/system design developing , validation and debugging.

Lead the design of NAND flash IO circuits, ensuring optimal performance and reliability. Demonstrate proficiency in basic analog circuit design concepts, including LDO, DCDC, BANDGAP, Voltage Detector, PLL, ADC, etc. Collaborate in conducting fail sample analysis and contribute to IC measurements to identify and address potential issues. If you have experience in NAND flash IO circuit design, a strong foundation in analog circuit design, and skills in fail sample analysis and IC measurement, we

我們正在招募一位 室內設計師 加入我們的團隊，尋找具備創意思維和室內設計經驗的夥伴。這個職位需要有至少三年以上室內設計的工作經驗，您將參與有趣的專案，挑戰傳統，為客戶創造充滿

1. Facilitate collaboration between foundries and teams in Japan or Taiwan. 2. Maintain seamless communication channels with foundries regarding CP/FT-related updates. 3. Track product yield performance across various technologies and provide reports to headquarters. 4. Collaborate with headquarters and foundries to identify strategies for improving product yield. 5. Troubleshoot issues during mass production and collaborate with headquarters and foundries to sustain yield levels. 6. Gather tech

面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

• 面板驅動IC 或 SoC 設計

負責 高速 PLL 以及 Serdes 相關類比電路開發。 設計PCIe/USB/SATA相關APHY serdes電路，例如：USB4、PCIe5、25G serdes

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh