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1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.

參與SSD韌體專案開發，進行硬體控制器的設計和實現，以達到高性能和高可靠性的要求。 參與新功能的研發並進行性能評估，確保SSD韌體的不斷優化。 與HW Engineer 密切合作確保專案順利執行。

studio with a vision to create innovative and engaging games for a global audience. We are looking for a talented and imaginative Level Designer to join our team and help us build immersive and unforgettable worlds. About the role: As a Level Designer, you will be responsible for crafting the very spaces where players will experience our games. You will: Design engaging and challenging levels that fit seamlessly with the overall game design. Create compelling n

Lead the design of NAND flash IO circuits, ensuring optimal performance and reliability. Demonstrate proficiency in basic analog circuit design concepts, including LDO, DCDC, BANDGAP, Voltage Detector, PLL, ADC, etc. Collaborate in conducting fail sample analysis and contribute to IC measurements to identify and address potential issues. If you have experience in NAND flash IO circuit design, a strong foundation in analog circuit design, and skills in fail sample analysis and IC measurement, we

1. Facilitate collaboration between foundries and teams in Japan or Taiwan. 2. Maintain seamless communication channels with foundries regarding CP/FT-related updates. 3. Track product yield performance across various technologies and provide reports to headquarters. 4. Collaborate with headquarters and foundries to identify strategies for improving product yield. 5. Troubleshoot issues during mass production and collaborate with headquarters and foundries to sustain yield levels. 6. Gather tech

Product platform HW system design integration Schematic design, PCB layout design and review RFQ/PRD research and feedback Component survey and technology study BOM creation and maintenance Circuit/system design developing , validation and debugging.

面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

Sentinel is producing a security system powered by deep learning that can evaluate threats on a property. The system is designed to consume video streams and other contextual information to analyze threats facing a home. The service creates an intelligent surveillance zone out to the perimeter of a property. We can identify potential threats in under 30 seconds & call the police. The Role Reporting to the Controller, Deep Sentinel is looking for a Customer Service & Collections

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh