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Logo of CakeResume Headhunting Recruitment Service.
1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
IP Integration
IP Design
Digital IC
1.8 jt ~ 2.5 jt TWD / tahun
Diperlukan pengalaman selama 3 tahun
Tidak ada tanggung jawab manajemen
Logo of 宏正自動科技股份有限公司.
將有專業培訓與指導,深入各式影像介面應用,並參與各項產品規格及系統設計規劃。成為專業的數位 IC 研發工程師,與我們一同開創科技趨勢新局! 【工作內容】 As a IC Design Engineer, you will design, implement and verify products that use FPGAs
40 rb ~ 80 rb TWD / bulan
Tidak ada persyaratan pengalaman kerja terkait
Tidak ada tanggung jawab manajemen
Logo of CakeResume Headhunting Recruitment Service.
2.5 jt ~ 3.5 jt TWD / tahun
Diperlukan pengalaman selama 5 tahun
Tidak ada tanggung jawab manajemen
Logo of CakeResume Headhunting Recruitment Service.
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
IC Designer
Top integrator
SoC
1.8 jt ~ 3 jt TWD / tahun
Diperlukan pengalaman selama 1 tahun
Tidak ada tanggung jawab manajemen
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
4 jt ~ 5 jt TWD / tahun
Diperlukan pengalaman selama 6 tahun
Mengatur 1-5 staf
Logo of CakeResume Headhunting Recruitment Service.
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus
Digital IC Designer
IC design
Memory
1.5 jt ~ 2.5 jt TWD / tahun
Diperlukan pengalaman selama 3 tahun
Tidak ada tanggung jawab manajemen
Logo of WASAI Technology.
* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills
OpenCL
Verilog
VHDL
80 rb ~ 200 rb TWD / bulan
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Tidak ada tanggung jawab manajemen
Logo of Morgan Philips Group.
【工作內容】 Maintain並整合USB3.2/USB4/PCIE MAC相關IP與Peripheral Design 驗證USB3.2/USB4/PCIE相關IP
1 jt ~ 3 jt TWD / tahun
Diperlukan pengalaman selama 1 tahun
Tidak ada tanggung jawab manajemen
Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 密碼演算法開發 2. 數位電路設計 (RTL) 3. 數位電路驗證 (UVM) 4. FPGA建置整合及驗證 -------------------------------------------------------------------------- 1. Crypto algorithm development 2. RTL design 3. UVM verification 4.
Linux
UNIX
40 rb+ TWD / bulan
Diperlukan pengalaman selama 3 tahun
Tidak ada tanggung jawab manajemen
Logo of MediaTek 聯發科技.
PCIe/USB/MIPI-CSI/Display Port 相關之高速介面ditigal PHY IC設計
Career in Taiwan
理科生
35 rb ~ 200 rb TWD / bulan
Diperlukan pengalaman selama 1 tahun
Tidak ada tanggung jawab manajemen

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