Hsieh Azure
R&D process integration engineer
Graduated with a master's degree in Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D process integration engineer in UMC about 7.7 years of experience; and process integration engineer in TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device
reliability improvement.
Email : [email protected]
Phone: 0910-828-616
UMC
National Yang Ming Chiao Tung University
Tainan, 台灣
专业背景
- 目前状态待业中・目前没有兴趣寻找新的机会
- 专业电子工程师・制程工程师・I&C 工程师
- 产业电子 / 电信・奈米科技・半导体
- 工作年资10 到 15 年 (10 到 15 年相关工作经验)
- 管理经历无
- 技能
- 语言能力English・中阶Japanese・初阶
- 最高学历硕士
求职偏好
- 预期工作模式全职・对远端工作有兴趣
- 希望获得的职位Semiconductor Engineer
- 期望的工作地点Tainan, Taiwan・Kaohsiung City, 台灣
- 接案服务不提供接案服务
工作经验
R&D process integration engineer
台灣台南市
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process develop, yield ramp up and reliability improve. EM life time reach 10,000 years in 1000ppm for specify customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process develop, include rule and test key design
3. 22nm eHV (device operate in 8V-27V) interconnect process develop
Process integration engineer
台灣台南市
Process integration engineer in 40nm - 90nm mature technology
1. Customer handling ( include new tape-out, low yield analysis, WAT, SPC chart monitor...etc)
2. 20nm process transfer from Hsinchu to Tainan
学历
Master’s Degree
・
Electrical Engineering & IC design简介
Research topic: A Digital Calibration Scheme for the Successive Approximation Analog-to-Digital Converter
Bachelor’s Degree
・
Electrical Engineering Department