Hsieh Azure
R&D process integration engineer
Graduated with a master's degree in Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D process integration engineer in UMC about 7.7 years of experience; and process integration engineer in TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device
reliability improvement.
Email : [email protected]
Phone: 0910-828-616
UMC
National Yang Ming Chiao Tung University
Tainan, 台灣
專業背景
- 目前狀態待業中・目前沒有興趣尋找新的機會
- 專業電子工程師・製程工程師・I&C 工程師
- 產業電子 / 電信・奈米科技・半導體
- 工作年資10 到 15 年 (10 到 15 年相關工作經驗)
- 管理經歷無
- 技能
- 語言能力English・中階Japanese・初階
- 最高學歷碩士
求職偏好
- 預期工作模式全職・對遠端工作有興趣
- 希望獲得的職位Semiconductor Engineer
- 期望的工作地點Tainan, Taiwan・Kaohsiung City, 台灣
- 接案服務不提供接案服務
工作經驗
R&D process integration engineer
台灣台南市
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process develop, yield ramp up and reliability improve. EM life time reach 10,000 years in 1000ppm for specify customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process develop, include rule and test key design
3. 22nm eHV (device operate in 8V-27V) interconnect process develop
Process integration engineer
台灣台南市
Process integration engineer in 40nm - 90nm mature technology
1. Customer handling ( include new tape-out, low yield analysis, WAT, SPC chart monitor...etc)
2. 20nm process transfer from Hsinchu to Tainan
學歷
Master’s Degree
・
Electrical Engineering & IC design簡介
Research topic: A Digital Calibration Scheme for the Successive Approximation Analog-to-Digital Converter
Bachelor’s Degree
・
Electrical Engineering Department