Research Direction: IC Packaging, FOWLP(Fan-out wafer level package),Wafer warpage, Process emulation 1. Established the semi-analytical model as the quick and effective evaluation to predict warpage and onset bifurcation temperature in FOWLP. 2. Developed equivalence bi-layer structural simplified FE model for predicting wafer warpage,comparing with standard reference which can reduce more than 60% computational cost with just 5% error. 3. Planned the DOE (Design of Experiment) of specimen to verify the accuracy of FEM and semi-analytical models. 4. Designed the processes emulator considering packaging materials characteristics to emulate the process flow for both chip-first and chip-last process. 5. Developed the optimization flow for evaluating appropriate parameters of FOWLP in early design stage of product.

Intern in SAA (迅得機械) 1.Utilized a photoelectric sensor to measure the angle error between the six-axis robotic arm and the printed circuit board. 2.Developed the calibration system and integrated into production line to improve production yield rate.