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製程工程師 @台灣美光記憶體股份有限公司2021 ~ Present
・
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
Within one month
Employed
・
Ready to interview
Full-time / Interested in working remotely
4-6 years
國立雲林科技大學
・
化學工程與材料工程
Past
資深應用工程師 @添鴻科技股份有限公司2022 ~ 2024
・
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
Within one month
王亦翰 (Eason Wang) Since the beginning of work in 2013/9 to present with 10.5 years experience as an engineer. Main expertise is yield improvement, process technology and new product evaluate, and also handle customer complaint investigation. In my current position at CLC company as Sr.Application engineer in Sales Division. Contact information: E-mail: [email protected] Mobile:CAREER SUMMARY With 7.5-years experiences as engineer in Semiconductor Industry, mainly focus on yield improvement, process technical, new product evaluation, and handle customer complaint investigation. Familiar
Unemployed
・
Ready to interview
Full-time / Interested in working remotely
6-10 years
國立雲林科技大學 National Yunlin University of Science and Technology
・
材料科技研究所Past
製程工程師 @漢民科技股份有限公司2020 ~ 2023
・
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
Within one month
Unemployed
・
Ready to interview
Full-time / Interested in working remotely
4-6 years
國立台灣師範大學
・
化學Open to opportunities
Full-time / Not interested in working remotely
4-6 years
國立台灣大學
・
生物材料
Past
Senior Engineer @ASUS 華碩電腦股份有限公司2018 ~ 2023
・
研發工程師、製程整合工程師、分析工程師、機構工程師、熱傳工程師
Within six months
參與的專案: 1.ASUS X507 (塑膠低成本機種，產量大) 2.ASUS X540 (塑膠低成本機種，產量大) 3.ASUS UX563FD (Flip/高跟鞋機種，鋁皮鎂鋁骨，NCVM製程) 4.ASUS E410MA (塑膠低成本機種，產量大) 5.ASUS N7401ZE (鋁皮塑骨機種，設計精美) 工作內容: 1.從事Laptop機構設計、ProE 3D,2D Drawing。 2.BOM
Unemployed
Full-time / Interested in working remotely
4-6 years
National Formosa University (NFU)
・
Department of Power Mechanical Engineering
Past
二級工程師 @Garmin Ltd. 台灣國際航電股份有限公司2022 ~ 2023
・
前端工程師
Within one month
吳冠興 (Felix Wu) [email protected] | https://github.com/xeaiow 工作經歷 製程整合部 / 二級工程師 E3 / GARMIN / 新北市 2022/9 ~ 2023/4 JavaScript( Next.js ) / Jest / Playwright 製作 Mockup UI 及參與 自動化 倉儲流程設計 將現有系統導入 Unit Test 與 End-To-End Test 增加穩定性、可靠性 研發部 / 資深工程
Unemployed
・
Not open to opportunities
Full-time / Interested in working remotely
4-6 years
中原大學
・
資訊管理所
製程工程師 @Genesis Photonics2020 ~ Present
・
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
More than one year
Wun-Shan Jhou Passionate about the optoelectronics semiconductor industry & enthusiast of automotive Tainan City，[email protected] Education Kun Shan University , Master's degree, Graduate School of Electro-Optical Engineering, 2014 ~ 2016 Graduating in the honor of the top-rated prize%) Kun Shan University, Bachelors' degree Department of Electro-Optical Engineering, 2010 ~ 2014 Graduating in the honor of the third best grading prize.(5.88%) Work Experience Genesis Photonics , Process Engineer, Dec 2020 ~ Now Process engineers, Responsible for process optimization and yield improvement Lithography Process Engineer mini LED photolithography technology Evaluation of introduction of photoresist Batch
Employed
Full-time / Interested in working remotely
4-6 years
崑山科技大學
・
光電工程
Active
Active
資深產品工程師 @Dialog Semiconductor 德商戴樂格半導體有限公司台灣分公司2022 ~ Present
・
工程師
Within one month
陳嘉豪 資深主任製程整合工程師 6年半導體製程經驗 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶 掌管全廠最大量產品BCD 成功改善超過40餘起案件 完成2項公司A級專案 訂定超過60餘項最佳化條件(BKM) 熟悉多台機台操作 新竹縣竹北市 [email protected]工作經歷
Employed
Full-time / Interested in working remotely
6-10 years
國立交通大學 National Chiao Tung University
・
電子工程
工程師 @台灣神隆股份有限公司2021 ~ Present
・
工程師
More than one year
photoresist coating - Production management 一月七月 2018 製程工程師 奇美視像科技股份有限公司 奇美材料公司的部分部門移轉至子公司奇美視像 1.LIGA製程-NIL無接縫圓筒之製程整合 2.無接縫圓筒之製程開發與改善 3.電解板凸提升工作板良率 4.開發新產品製程
Employed
Full-time / Interested in working remotely
4-6 years
國立成功大學
・
機械工程系
Past
製程整合資深工程師 @矽品精密股份有限公司2016 ~ 2020
・
半導體製程工程師,半導體製程整合工程師,半導體研發工程師
More than one year
物 喜歡動腦思考，如何將事情做到最好 喜歡團隊合作，分工合作會走得更遠 喜歡解決問題，享受完事後的成就感 工作經歷 製程整合資深工程師 矽品精密股份有限公司 十一月十月 2020Taipei, Taiwan 主要作為公司與客戶間的橋樑，負責協調工廠內各資源以
Unemployed
Full-time / Remote Only
4-6 years
國立中興大學
・
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Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
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Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
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Leadership
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Professional Background
Current status
Employed
Job Search Progress
Professions
Process Engineer
Fields of Employment
Semiconductor
Work experience
6-10 years
Management
None
Skills
Languages
English
・
Professional
Job search preferences
Positions
工程師
Job types
Full-time
Locations
台灣新竹市
Remote
Interested in working remotely
Freelance
No
Educations
School
國立交通大學 National Chiao Tung University
Major
電子工程
陳嘉豪
資深主任製程整合工程師
- 6年半導體製程經驗
- 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
- 掌管全廠最大量產品BCD
- 成功改善超過40餘起案件
- 完成2項公司A級專案
- 訂定超過60餘項最佳化條件(BKM)
- 熟悉多台機台操作
新竹縣竹北市
+886 0989-929-413
工作經歷
UMC 聯華電子 - 資深主任製程整合工程師
一月 2017 - Present (5年)
- 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
- 負責產品：BCD(全廠最大產量)、Logic
- 工作內容：
- 開發新平台(Platform)
- 改善跨製程問題
- WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
- 監控線上產品
- 導入新產品
- 客戶專案的推動 / 執行
- 回覆客戶問題及處理客訴
- 成就 / 貢獻：
- 成功改善40餘起案子，其中超過20項重大案件
- HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
- 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
- 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
- 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
- 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
- 熟悉多台機台操作
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
- 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定
- 成功改善40餘起案子，其中超過20項重大案件
碩士學歷
Micron 美光科技 - 高級缺陷改善工程師
一月 2016 - 十二月 2016 (1年)
- 負責產品：SI(Silicon interposer)
- 工作內容：
- 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
- 跨部門專案的推動 / 執行
- 跨部門合作改善缺陷數量
- 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 成就 / 貢獻：
- 成功解決影響全廠的Wafer edge low yield issue
- 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 熟悉SEM, EDS, Leica機台操作
國立交通大學 - 電子工程學研究所
國立中央大學 - 化學工程與材料工程學研究所
指導教授：侯拓宏, 周正堂 教授
GPA：3.8/4
期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)
實驗地點：國家實驗研究院(NARLabs)
成就 / 貢獻：
- 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
- 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程
2012 - 2014
2012 - 2014
技能
- 半導體製程
- 半導體物理
- 半導體材料
- 電性分析
- 電性量測(DC/TLP SOA)
- 良率分析
- 資料統計分析
- 風險評估分析及應對策略擬定
- BCD 製程
- BCD 元件分析
擅長工具
Excel PowerPoint Word
語言
- 中文
- 英文 - TOEIC：760
Jia-Hao Chen
Senior Principal Process Integration Engineer(PIE)
- 6 years' experience in semiconductor field
- Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- In charge of the product BCD with maximum output in the whole factory
- Successfully improved more than 40 cases
- Finished 2 of our company's top projects
- Defined more than 60 best known methods(BKM)
- Specialize in operating numerous equipment
Hsinchu, Taiwan
+886 0989-929-413
Work Experience
UMC - Senior Principal Process Integration Engineer
Jan., 2017 - Present (5 Years)
- Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- Product：BCD(With maximum output), Logic
- Job Description：
- Develop new platforms
- Improve cross-process issues
- Analyze / Improve / Track / Prevent WAT abnormalities and low yields
- Monitor products on the production line
- Import new products
- Promote / Execute client’s projects
- Respond to client’s problems and handle client complaints
- Achievement / Contribution：
- Successfully improved more than 40 cases, including more than 20 serious cases
- HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
- Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
- Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
- Defined more than 60 best known methods(BKM) to strengthen the BCD process
- Investigated countless WAT SPC alarms
- Specialize in operating numerous equipment
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
- Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors
- Successfully improved more than 40 cases, including more than 20 serious cases
Micron - Senior Defect Engineer
Jan., 2016 - Dec., 2016 (1 Year)
- Product：SI(Silicon interposer)
- Job Description：
- Analyze / Improve / Track / Prevent abnormal defects
- Promote / Execute cross-department projects
- Cross-departmental cooperation to improve the defect level
- Establish defect specification / category
- Achievement / Contribution：
- Successfully resolved the wafer edge low yield issue affecting the entire factory
- Established the first defect specification / category in our department
- Expert in operating SEM, EDS, Leica
Master’s Experience
National Chiao Tung University - Electronics Engineering
National Central University - Chemical and Materials Engineering
Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou
GPA：3.8 / 4
Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation
Laboratory：National Applied Research Laboratories(NARLabs)
Achievement / Contribution：
- Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
- Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow
2012 - 2014
2012 - 2014
Skills
- Semiconductor Process
- Semiconductor Physics and Devices
- Semiconductor Materials
- Electrical Analysis
- Electrical Measurement (DC/TLP SOA)
- Yield Analysis
- Data Statistical Analysis
- Risk Assessment and Strategy Formulation
- BCD Process
- BCD Device Analysis
Tools
Excel PowerPoint Word
Language
- Chinese
- English - TOEIC：760
陳嘉豪
資深主任製程整合工程師
- 6年半導體製程經驗
- 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
- 掌管全廠最大量產品BCD
- 成功改善超過40餘起案件
- 完成2項公司A級專案
- 訂定超過60餘項最佳化條件(BKM)
- 熟悉多台機台操作
新竹縣竹北市
+886 0989-929-413
工作經歷
UMC 聯華電子 - 資深主任製程整合工程師
一月 2017 - Present (5年)
- 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
- 負責產品：BCD(全廠最大產量)、Logic
- 工作內容：
- 開發新平台(Platform)
- 改善跨製程問題
- WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
- 監控線上產品
- 導入新產品
- 客戶專案的推動 / 執行
- 回覆客戶問題及處理客訴
- 成就 / 貢獻：
- 成功改善40餘起案子，其中超過20項重大案件
- HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
- 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
- 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
- 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
- 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
- 熟悉多台機台操作
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
- 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定
- 成功改善40餘起案子，其中超過20項重大案件
碩士學歷
Micron 美光科技 - 高級缺陷改善工程師
一月 2016 - 十二月 2016 (1年)
- 負責產品：SI(Silicon interposer)
- 工作內容：
- 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
- 跨部門專案的推動 / 執行
- 跨部門合作改善缺陷數量
- 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 成就 / 貢獻：
- 成功解決影響全廠的Wafer edge low yield issue
- 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 熟悉SEM, EDS, Leica機台操作
國立交通大學 - 電子工程學研究所
國立中央大學 - 化學工程與材料工程學研究所
指導教授：侯拓宏, 周正堂 教授
GPA：3.8/4
期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)
實驗地點：國家實驗研究院(NARLabs)
成就 / 貢獻：
- 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
- 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程
2012 - 2014
2012 - 2014
技能
- 半導體製程
- 半導體物理
- 半導體材料
- 電性分析
- 電性量測(DC/TLP SOA)
- 良率分析
- 資料統計分析
- 風險評估分析及應對策略擬定
- BCD 製程
- BCD 元件分析
擅長工具
Excel PowerPoint Word
語言
- 中文
- 英文 - TOEIC：760
Jia-Hao Chen
Senior Principal Process Integration Engineer(PIE)
- 6 years' experience in semiconductor field
- Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- In charge of the product BCD with maximum output in the whole factory
- Successfully improved more than 40 cases
- Finished 2 of our company's top projects
- Defined more than 60 best known methods(BKM)
- Specialize in operating numerous equipment
Hsinchu, Taiwan
+886 0989-929-413
Work Experience
UMC - Senior Principal Process Integration Engineer
Jan., 2017 - Present (5 Years)
- Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- Product：BCD(With maximum output), Logic
- Job Description：
- Develop new platforms
- Improve cross-process issues
- Analyze / Improve / Track / Prevent WAT abnormalities and low yields
- Monitor products on the production line
- Import new products
- Promote / Execute client’s projects
- Respond to client’s problems and handle client complaints
- Achievement / Contribution：
- Successfully improved more than 40 cases, including more than 20 serious cases
- HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
- Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
- Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
- Defined more than 60 best known methods(BKM) to strengthen the BCD process
- Investigated countless WAT SPC alarms
- Specialize in operating numerous equipment
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
- Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors
- Successfully improved more than 40 cases, including more than 20 serious cases
Micron - Senior Defect Engineer
Jan., 2016 - Dec., 2016 (1 Year)
- Product：SI(Silicon interposer)
- Job Description：
- Analyze / Improve / Track / Prevent abnormal defects
- Promote / Execute cross-department projects
- Cross-departmental cooperation to improve the defect level
- Establish defect specification / category
- Achievement / Contribution：
- Successfully resolved the wafer edge low yield issue affecting the entire factory
- Established the first defect specification / category in our department
- Expert in operating SEM, EDS, Leica
Master’s Experience
National Chiao Tung University - Electronics Engineering
National Central University - Chemical and Materials Engineering
Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou
GPA：3.8 / 4
Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation
Laboratory：National Applied Research Laboratories(NARLabs)
Achievement / Contribution：
- Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
- Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow
2012 - 2014
2012 - 2014
Skills
- Semiconductor Process
- Semiconductor Physics and Devices
- Semiconductor Materials
- Electrical Analysis
- Electrical Measurement (DC/TLP SOA)
- Yield Analysis
- Data Statistical Analysis
- Risk Assessment and Strategy Formulation
- BCD Process
- BCD Device Analysis
Tools
Excel PowerPoint Word
Language
- Chinese
- English - TOEIC：760