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4-6 years
6-10 years
10-15 years
More than 15 years
Senior Engineer @Powertech Technology Inc.2021 ~ Present
・
Senior Engineer
More than one year
Employed
・
Not open to opportunities
Full-time / Interested in working remotely
4-6 years
國立雲林科技大學 National Yunlin University of Science and Technology
・
Electrical Engineering
Past
Support Engineer @ Astrata Europe (formerly Qualcomm Business Solutions Europe2007 ~ 2014
・
Customer Support
More than one year
Manufacturing Engineer is to guard the process of building, adjusting and qualifying a NPI (New Product Introduction) type of machine with regards to Cycle Time CT: - Identify current/former product actual KPI values: Availability, Cycle Time, part failures, errors, downtimes. - Conduct in a mutli-disciplinary team the FMEA analysis . - Review design documentations and add -up industrialization requirements. - Write the impact analysis doc and support the fab with the right tools, building instructions, plant availability, mechanics, product design, knowledge. - Create blue print in SAP ME for the machine blocks assembling sequence order. - Write assembling procedures
Unemployed
Full-time / Not interested in working remotely
10-15 years
Technical University of Orleans (France)
・
Applied physicsPast
產品開發工程師/EPM @鴻來企業股份有限公司2018 ~ 2023
・
半導體工程師/PM/產品經理/專案管理
Within six months
Unemployed
Full-time / Interested in working remotely
4-6 years
私立中國文化大學
・
機械工程學
Cloud Service Provider - SSD engineer @Lenovo_台灣聯想環球科技股份有限公司2022 ~ Present
・
Within six months
technical documents and (8D) failure analysis report Provide technical support for customers in the development stage. Provide training to Sales and FAE of oversea branches. (Japan, Europe, Middle East area and Taiwan) [Taiwan semiconductor Inc] JUL.2015–Oct.2017AE Section Manager Lead 5 team members to implement failure analysis and determine root cause. Interface suppliers andmonitor production quality,production record and make the improvement be done. Create and audit 8D report and failure analysis report Deal with customer complaint and technical inquiry Provide technical support directly and feedback for major customers...
Employed
Full-time / Interested in working remotely
6-10 years
國立宜蘭大學National Ilan University
・
Electrical Engineering
Customer Service Deputy Manager @欣興電子股份有限公司2023 ~ Present
・
SQE
Within one month
Ares Huang Deputy Manager at Unimicron Technology Corp. Have more than 6 years of customer/ quality management experience of PCB in Apple's supply chain. Familiar with the knowledge and tool of 8D failure mode analysis and solve quality issue. Taoyuan City, Taiwan 工作經歷 Quality Service Deputy Manager • 欣興電子股份有限公司 Responsible for managing PCB issue for Apple Macbook/ iPad/ Tcon/ Accessiores project Serve as the primary contact window for customers regarding PCB assembly processes and quality assurance. In the event of
Employed
・
Open to opportunities
Full-time / Interested in working remotely
6-10 years
National Taiwan Ocean University
・
Marine biology
FAE Assistant Manager @UD info CORP.2018 ~ Present
・
Product Manager
Within three months
Using an oscilloscope, logic analyzer measurement signal to solved many compatibility problems. Regularly visit various MB manufacturers, gathering the latest information To the client educate customers on how to design DRAM, explain Datasheet EXPERIENCE TAIWAN Wistron COMPANY Hsin-Chu County Work in the Wistron as global quality and failure analysis department, Senior Application Engineer For NB, Server, PC ,DTV etc, has in fact analysis and writing 8D report and use 8D way to solve problems in the factory production line. TAIWAN Silicon-Power COMPANY Taipei County Worked at Silicon Power FAE section manager. In March 2012 sent
Employed
Full-time / Interested in working remotely
More than 15 years
National Dong Hwa University, NDHU
・
RRAM
Product Manager @喬山健康科技股份有限公司2022 ~ Present
・
Project Manager、PM、專案經理、UX、網站企劃、產品企劃
Within six months
Ltd. Songson Hardware Co. Ltd. ODM/JDM: Optimized customer demand progress design, structure design, Narimoto report, strike, functional test, various materials and joint services, DVT/EVT, product assembly distribution, product packaging distribution. Company-owned development: new product design and development, new product market failure analysis. Product functional problem elimination: quantity product quality, functional problem research/experiment/improvement, production 8D report, etc. Market analysis: market external competitor analysis, product market positioning analysis, product labeling strategy analysis. Planning management: Controlling the timing of discussion with guests, managing the timing of each
Employed
Full-time / Interested in working remotely
6-10 years
國立雲林科技大學 National Yunlin University of Science and Technology
・
工業設計Unemployed
・
Ready to interview
Full-time / Interested in working remotely
6-10 years
大葉大學 DaYeh University
・
電機工程學系
ERP資訊工程師-ERP Software Engineer @南茂科技股份有限公司 ChipMOS TECHNOLOGIES2022 ~ Present
・
Engineer, SA, SD, Data Analyst, PM
Within one month
SVN、VSS 資料庫： Oracle DB、Oracle DB Gateways、SQL Server、SQLite 伺服器&虛擬化： IIS、Nginx、Windows Server、Windows CE、Solaris、VirtualBox ML&DL： YOLO、Darknet、Pandas、Seaborn 管理分析相關： 專案管理、IT治理服務管理、8D Report、統計分析、Excel、Tableau 其它： SoftwareAG webMethods 、SAP、救護技能、財務會計 工作經歷 ERP資訊工程師-ERP Software Engineer 南茂科技股份有限公司 ChipMOS TECHNOLOGIES • 十二月至
Employed
・
Open to opportunities
Full-time / Interested in working remotely
6-10 years
國立成功大學 National Cheng Kung University
・
Industrial and Information Management
資深工程師 @NOKIA2020 ~ Present
・
python 後端工程師
Within one month
PO Yuan Chiu Taipei City, [email protected] https://www.linkedin.com/in/%E5%8D%9A%E9%81%A0-%E9%82%B1-a8a58999/ https://twitter.com/pauiCurrently working at NOKIA as an analytical system development backend using DJANGI CELERY REDIS MYSQL, etc. work experience Senior python software engineer NOKIA 四月Present | Taipei, Taiwan Base Station Big Data Analysis System Developed and maintained using Django + Django DRF + Celery + Redis Added RESTful API Increased scalability Developed each subsystem in detail Migrated the system from
Employed
Full-time / Interested in working remotely
4-6 years
崑山科技大學
・
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Within one year
Process Integration Engineer @ Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
・
2014 ~ Present
Professional Background
Current status
Job Search Progress
Professions
Other
Fields of Employment
Manufacturing
Work experience
4-6 years
Management
Skills
Languages
Chinese
・
Native or Bilingual
English
・
Fluent
Japanese
・
Beginner
Job search preferences
Positions
Product Engineer
Job types
Full-time
Locations
Hsinchu County, 台灣
Remote
Interested in working remotely
Freelance
Educations
School
Cheng Kung University
Major
Electrical Engineering
林庭揚 (Ting Yang, Lin)
Over 7 years of semiconductor integration experience, and successful Tape-Out new products to 5nm from 90nm and mass production (including logic and more than moore products). Successfully improve product yield through data analysis and DOE, and enhance process tolerance. "Teamwork" is very important to me both in the graduate school and in the company. I hope that I have opportunity to try my best for your company with my extensive experience.
Process Integration Engineer, TSMC,
Tainan, Taiwan
[email protected]
+886 963958505
Skills
Semiconductor (5nm~90nm)
- Device engineering
- Semiconductor Process
- WAT Analysis
- Yield Analysis
- Process Quality Test
Manufacturing
- Statistical Process Control (SPC)
- Cp/Cpk
- Failure Mode and Effects Analysis (FMEA)
- Design of Experiments (DOE)
- PDCA
- 3-Leg-5-Why
- 8D
- Pareto Chart
- Box Plot & Normal Quantile Plot
Failure Analysis Tool
- JMP software
- Transmission Electron Microscopy (TEM)
- Energy-dispersive X-ray spectroscopy (EDX)
Work Experience
TSMC, Process Integration Engineer Nov 2014 ~ Present
- 5nm process experience for new product tape-out, yield/device improvement, process optimization and risk assessment.
- More than moore products' experience including 40/55/80nm high voltage (panel driver),
90nm eDRAM and 65nm automotive products.
- Yield/ device troubleshooting in semiconductor process and coordinating cross team (Module/ Device/ Defect/ Product) to propose possible solution.
- Design, execute and analyze experiment to find out process sweet spot for process window assurance.
- Good for customer management: technical support, successful new tape-out pilot run, device window optimization and continue improvement plan.
- Mass data analysis: inline/WAT/CP/FT data integrated analysis by EDA tool -- Implement FA skill for chip failure mechanism analysis, such as FIB/SEM/TEM/EDX,etc.
Award & Honor (TSMC)
- 2019 1H Engineering Contribution Award (Quality Improvement), 2nd Award, 2019
- Success tape-out customer 1st 40nm HV product, yield is over 90%, and pass customer product quality test.
- (5nm) Found wafer edge low yield caused by rework effect
- (5nm) Found chronic wafer center low yield caused by device profile and tool issue
- (40nm) Found and reduce the device leakage.
- (55nm) Improve wafer edge yield loss due to leakage and process weakness by wafer uniformity increment.
Education
National Cheng Kung University (NCKU)
Master's Degree, Electrical and Electronics Engineering, 2012 ~ 2014
Design and Verification of the Control Procedure of Attitude Determination and Control Subsystem for Nanosatellite.
- Participate 1st cubesat (PACE) make and launch
- Japan Satellite Design Contest: lead graduate and college students to do engineering design
- Phoenix (QB50 project): Be responsible for attitude determination and control system
- Matlab teaching assistant
National Cheng Kung University (NCKU)
Bachelor's's Degree, Systems and Naval Mechatronic Engineering, 2008 ~ 2012
Award & Honor (NCKU)
- The 20th Japan Satellite Design Contest, 1st Award, 2012
- Participate to manufacture 1st nanosatellite by students.
林庭揚 (Ting Yang, Lin)
Over 7 years of semiconductor integration experience, and successful Tape-Out new products to 5nm from 90nm and mass production (including logic and more than moore products). Successfully improve product yield through data analysis and DOE, and enhance process tolerance. "Teamwork" is very important to me both in the graduate school and in the company. I hope that I have opportunity to try my best for your company with my extensive experience.
Process Integration Engineer, TSMC,
Tainan, Taiwan
[email protected]
+886 963958505
Skills
Semiconductor (5nm~90nm)
- Device engineering
- Semiconductor Process
- WAT Analysis
- Yield Analysis
- Process Quality Test
Manufacturing
- Statistical Process Control (SPC)
- Cp/Cpk
- Failure Mode and Effects Analysis (FMEA)
- Design of Experiments (DOE)
- PDCA
- 3-Leg-5-Why
- 8D
- Pareto Chart
- Box Plot & Normal Quantile Plot
Failure Analysis Tool
- JMP software
- Transmission Electron Microscopy (TEM)
- Energy-dispersive X-ray spectroscopy (EDX)
Work Experience
TSMC, Process Integration Engineer Nov 2014 ~ Present
- 5nm process experience for new product tape-out, yield/device improvement, process optimization and risk assessment.
- More than moore products' experience including 40/55/80nm high voltage (panel driver),
90nm eDRAM and 65nm automotive products.
- Yield/ device troubleshooting in semiconductor process and coordinating cross team (Module/ Device/ Defect/ Product) to propose possible solution.
- Design, execute and analyze experiment to find out process sweet spot for process window assurance.
- Good for customer management: technical support, successful new tape-out pilot run, device window optimization and continue improvement plan.
- Mass data analysis: inline/WAT/CP/FT data integrated analysis by EDA tool -- Implement FA skill for chip failure mechanism analysis, such as FIB/SEM/TEM/EDX,etc.
Award & Honor (TSMC)
- 2019 1H Engineering Contribution Award (Quality Improvement), 2nd Award, 2019
- Success tape-out customer 1st 40nm HV product, yield is over 90%, and pass customer product quality test.
- (5nm) Found wafer edge low yield caused by rework effect
- (5nm) Found chronic wafer center low yield caused by device profile and tool issue
- (40nm) Found and reduce the device leakage.
- (55nm) Improve wafer edge yield loss due to leakage and process weakness by wafer uniformity increment.
Education
National Cheng Kung University (NCKU)
Master's Degree, Electrical and Electronics Engineering, 2012 ~ 2014
Design and Verification of the Control Procedure of Attitude Determination and Control Subsystem for Nanosatellite.
- Participate 1st cubesat (PACE) make and launch
- Japan Satellite Design Contest: lead graduate and college students to do engineering design
- Phoenix (QB50 project): Be responsible for attitude determination and control system
- Matlab teaching assistant
National Cheng Kung University (NCKU)
Bachelor's's Degree, Systems and Naval Mechatronic Engineering, 2008 ~ 2012
Award & Honor (NCKU)
- The 20th Japan Satellite Design Contest, 1st Award, 2012
- Participate to manufacture 1st nanosatellite by students.