類比IC設計工程師 (Ethernet)

Ethernet

1. 10/100/1000 Ethernet PHY Design (具備ADC/DAC 設計經驗
2. Deliver document for SOC integration
3. Provide Analog IP MP solution in CP/FT.
4. Analog IP ES validation

1. MSEE with at least 3 years of industrial working experience.
2. Has experience of design/verification/debug DDR2/DDR3/LPDDR2/LPDDR3 (Data-Rate > 1.6Gbps) physical interface or DDR IO
3. Familiar with DDR JEDEC DDR2/DDR3/LPDDR2/LPDDR3 STANDARD
4. Familiar with HSPICE, Unix/Linux System, STA timing evaluation
5. Familiar with ESD conception
6. Has 40nm/28nm process of mass production experience
7. 應屆畢業生，碩論需為類比相關