數位IC驗證工程師R2

Verification for High Speed PHY projects, which includes:
1. Responsibility for test plans, testbench documentation and implementation.
2. Use SystemVerilog language, SVA and UVM methodology for block level verification.
3. Debug tests with design engineers to deliver functionally correct design blocks.
4. Close coverage measures to identify verification holes and show progress towards tape-out.
5. Write scripts to automate routine parts of verification workflow.

1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。
2. 具3年以上下列經驗之一者為佳：
(1) Experience verifying digital logic at RTL using SystemVerilog for FPGAs and/or ASICs.
(2) Experience verifying digital systems using standard IP components/interconnects.
(3) Experience creating and using verification components and environments in standard verification methodology.
3. Preferred qualifications:
(1) Experience with high speed MAC/PHY RTL design or verification.
(2) Experience with UVM methodology and coding.
(3) Good English verbal communication skills.