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Logo of MediaTek 聯發科技.
PCIe/USB/MIPI-CSI/Display Port 相關之高速介面ditigal PHY IC設計
Career in Taiwan
理科生
35K ~ 200K TWD / month
1 years of experience required
No management responsibility
Logo of MediaTek 聯發科技.
1. 高速SerDes IP開發 2. 數位電路設計與晶片整合 3. 訊號處理與通訊演算法實現
Logo of 晶豪科技 ESMT.
1. 設計感測處理器晶片的數位電路: 1) FIR/IIR digital filter design and implementation. 2) 32bit MCU AHB/DMA/UART/I2C/SPI/Timer/RTC/WDT/PIT/GPIO design. 3) digital/analog integration and co-simulation . 4) MAC design and optimization. 5) sensor algorithm development. 2. 開發測試程式: 數位
60K ~ 200K TWD / month
1 years of experience required
No management responsibility
Logo of MediaTek 聯發科技.
1. 數位 IC 設計 2. 高速 MAC/PCS/PHYD 設計 3. 高速電路架構與整合
Logo of 浦飛爾科技有限公司.
1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
780K ~ 2.34M TWD / year
No management responsibility
Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 密碼演算法開發 2. 數位電路設計 (RTL) 3. 數位電路驗證 (UVM) 4. FPGA建置整合及驗證 -------------------------------------------------------------------------- 1. Crypto algorithm development 2. RTL design 3. UVM verification 4.
Linux
UNIX
40K+ TWD / month
3 years of experience required
No management responsibility
Logo of 宏正自動科技股份有限公司.
數位 IC 研發工程師」,你將有專業培訓與指導,深入各式影像介面應用,並參與各項產品規格及系統設計規劃。成為專業的數位 IC 研發工程師,與我們一同開創科技趨勢新局! 【工作內容】 As a IC Design Engineer, you
40K ~ 80K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
IC Designer
Top integrator
SoC
1.8M ~ 3M TWD / year
1 years of experience required
No management responsibility
Logo of WASAI Technology.
* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills
OpenCL
Verilog
VHDL
80K ~ 200K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of Andes Technology 晶心科技.
1. Verify RISC-V SOC platform including bus fabric, peripheral IPs: SPI, UART, I2C, PWM…etc. 2. Build testbench, develop and maintain in-house VIP 3. Create rand constraint conditions, analysis coverage holes and fill them 4. Create function coverage points to make sure all functions are under test
Verilog
C
C++
50K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility

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