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Hsinchu City, Taiwan
Logo of NVIDIA.
NVIDIA is seeking outstanding entry-level Verification Engineers to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs by developing scalable testbench that is re-usable across different verification methodologies and environments. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing fiel
PCIE
ASIC
Verilog
2 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
Logo of Morgan Philips Group.
【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.
UVM
Verilog
Verification
Regular earnings reach NT$40,000
2 years of experience required
No management responsibility
Logo of Morgan Philips Group.
Job Responsibilities: Engage in RTL/Digital circuit design, synthesis, and simulation/verification. Conduct FPGA synthesis and verification processes. Manage chip integration, algorithm implementation, and interface design. Generate test patterns.
1M ~ 3M TWD / year
3 years of experience required
No management responsibility
Logo of NVIDIA.
We are now looking for a ASIC Verification Engineer - Coherent High Speed Interconnect! For two decades, we have pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research. Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU
Testbenches
C++
PCIE
5 years of experience required
No management responsibility
Logo of Andes Technology 晶心科技.
1. Verify RISC-V SOC platform including bus fabric, peripheral IPs: SPI, UART, I2C, PWM…etc. 2. Build testbench, develop and maintain in-house VIP 3. Create rand constraint conditions, analysis coverage holes and fill them 4. Create function coverage points to make sure all functions are under test
Verilog
C
C++
50K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 印正有限公司 Yins Corp.
The HW system application engineer is responsible for IC verification system platform development which is used for CMOS image sensor applications. Responsibilities include HW system circuit design, layout and manufacturing for IC characterization and verification. 需出差,一年累積時間未定。
40K ~ 200K TWD / month
3 years of experience required
No management responsibility
Logo of Ansys 安矽思科技股份有限公司.
Summary / Role Purpose The R&D Engineer contributes to the development of software products and supporting systems. In this role, the R&D Engineer will collaborate with a team of expert professionals to accomplish development objectives. Key Duties and Responsibilities · Performs basic development activities, including the design, implementation, maintenance, testing and documentation of software modules and sub-systems · Learns and employs best practices · Performs basic bug verification, relea
電子工程
電機工程
EDA
Regular earnings reach NT$40,000
3 years of experience required
No management responsibility
Logo of Ansys 安矽思科技股份有限公司.
Summary / Role Purpose The R&D Engineer contributes to the development of software products and supporting systems. In this role, the R&D Engineer will collaborate with a team of expert professionals to accomplish development objectives. Key Duties and Responsibilities · Performs basic development activities, including the design, implementation, maintenance, testing and documentation of software modules and sub-systems · Learns and employs best practices · Performs basic bug verification, relea
Perl
Python
TCL
Regular earnings reach NT$40,000
3 years of experience required
No management responsibility

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