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Logo of Ali Tech.
1.高速介面(SerDes)類比電路設計 2.Circuit design of CTLE/CDR/DFE/PLL/TX 3.Familiar with SerDes and DDR PHY architecture (ex: PCIe3 / USB3 / HDMI2 / DDR4 / LPDDR4/4x ...etc)
C++
FPGA
PLL
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of Ali Tech.
1. 具Bluetooth系統設計分析 2. Bluetooth產品設計專案規劃 3. 專案開發技術指導 4. 客戶參訪,技術方案支持及推廣
C++
Verilog
FPGA
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of 廣達電腦股份有限公司 .
1. 依所負責之功能或專案,進行系統硬體設計、功能驗證、測試製具開發、系統及主板開發文件撰寫、問題解決(x86系統為主)。 2. 跨單位合作解決產品各階段如試產、展示、量產之軟硬體問題以利產
X86
硬體工程技術開發
硬體系統研發設計
40K ~ 70K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 宏正自動科技股份有限公司.
發工程師,與我們一同開創科技趨勢新局! 【工作內容】 As a IC Design Engineer, you will design, implement and verify products that use FPGAs and/or ASICs. 1. Participate in the micro architecture and design partition within the FPGAs and/or ASICs and implement design blocks using Verilog. 2. Participate in all phases of FPGA/ASIC design Flow (Synthesis, Place & Rout
40K ~ 80K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 晶豪科技 ESMT.
器晶片的數位電路: 1) FIR/IIR digital filter design and implementation. 2) 32bit MCU AHB/DMA/UART/I2C/SPI/Timer/RTC/WDT/PIT/GPIO design. 3) digital/analog integration and co-simulation . 4) MAC design and optimization. 5) sensor algorithm development. 2. 開發測試程式: 數位功能的量測及FPGA
60K ~ 200K TWD / month
1 years of experience required
No management responsibility
Logo of 久元電子股份有限公司.
測試系統開發/維護能力 1. 硬體電路開發設計:類比電路設計、數位電路設計、電源模組設計 2. 韌體程式開發(FPGA/Verilog)
36K ~ 65K TWD / month
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Analog & Digital Circuits Design AC/DC,DC/DC power design 使用OrCad 繪製電路圖,DC/DC Power Designing, 設計包含電流自檢, 電壓自檢, OCP, OVP, OTP等電路,電路控制CPLD/FPGA, 負責FCT 專案的研發, Wireless Board 的設計 與客戶溝通達到客戶產品測試
700K ~ 1.8M TWD / year
6 years of experience required
No management responsibility
Logo of WASAI Technology.
* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform. * Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform. *You will join a growing team of digital IC design engineering professionals and have a real opportunity to have your hardware solutions
C
C++
OpenCL
80K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility

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