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Benjamin Wan
Digital IC Design Engineer
Digital Design Engineer, have been working in IC Design for more than 3 years.
Apart from the hardware design work, I also spend my time studying deep learning and robotics.
Allystar Technology Co. Ltd
The University of Hong Kong
Hong Kong
Professional Background
- Situación actual
- ProfessionData Engineer
- Fields
- Experiencia laboral2-4 años
- Management
- Skills
- LanguagesChinese・Nativo o bilingüeEnglish・Profesional
- Highest level of educationMaster
Job search preferences
- Desired job typeA tiempo completo・Interesado en trabajar a distancia
- Desired positionsIC Design Engineer; FPGA Engineer; Deep Learning
- Lugares de trabajo deseadosTaipei, Taiwan
- Freelance
Work Experience
Digital IC Design Engineer
-Worked for Baseband Technology Team of GPS SoC ASIC project
-Designed Fast Fourier Transform accelerator
-Used Python to design digital signal processing model for hardware design and testing
-Used C to implement embedded software ROM code for baseband debug and performance test
Digital Design Engineer
-Worked for Digital Design Team and helped to build LED display controller
-Designed 2D graphics controller for on-screen display
-Designed hardware bootloader for embedded processor
FPGA Design Engineer
-Supported the development and testing of company products
-Setup testing environment on ZYNQ Zedboard to evaluate Xilinx Video IP
-Created control module of Xilinx Video IP for the integration of the IP into image scaler accelerator product
Education
Master of Science (MS)
・
Electrical & Electronic EngineeringDescripción
Study:
-Machine Learning
-Deep Learning
-Data Mining
-Computer Vision
-Digital Signal Processing
Coursework:
-Brain MRI Segmentation using ResNet-V2 & Keras
-CIFAR-10 challenge using Inception Network & Keras
FYP:
-Deep learning application in autonomous mobile robot
Master of Science (MS)
・
Electrical & Electronic EngineeringDescripción
I studied 4 years covering the Bachelor and Master program
FYP:
-Work-stealing for ZYNQ FPGA
Applied work-stealing principle to design multi-thread scheduler in C++ to offload CPU work to FPGA