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Benjamin Wan
Digital IC Design Engineer
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Benjamin Wan

Digital IC Design Engineer
Digital Design Engineer, have been working in IC Design for more than 3 years. Apart from the hardware design work, I also spend my time studying deep learning and robotics.
Allystar Technology Co. Ltd
The University of Hong Kong
Hong Kong

職場能力評價

專業背景

  • 目前狀態
  • 專業
    數據工程師
  • 產業
  • 工作年資
    2 到 4 年
  • 管理經歷
  • 技能
    C++
    Verilog HDL
    Python
    Tensorflow (Keras)
    Linux
  • 語言能力
    Chinese
    母語或雙語
    English
    專業
  • 最高學歷
    碩士

求職偏好

  • 預期工作模式
    全職
    對遠端工作有興趣
  • 希望獲得的職位
    IC Design Engineer; FPGA Engineer; Deep Learning
  • 期望的工作地點
    Taipei, 台灣
  • 接案服務

工作經驗

Digital IC Design Engineer

2018年3月 - 現在
-Worked for Baseband Technology Team of GPS SoC ASIC project -Designed Fast Fourier Transform accelerator -Used Python to design digital signal processing model for hardware design and testing -Used C to implement embedded software ROM code for baseband debug and performance test

Digital Design Engineer

2017年1月 - 2017年12月
1 年 0 個月
-Worked for Digital Design Team and helped to build LED display controller -Designed 2D graphics controller for on-screen display -Designed hardware bootloader for embedded processor

FPGA Design Engineer

2015年12月 - 2016年7月
8 個月
-Supported the development and testing of company products -Setup testing environment on ZYNQ Zedboard to evaluate Xilinx Video IP -Created control module of Xilinx Video IP for the integration of the IP into image scaler accelerator product

學歷

Master of Science (MS)
Electrical & Electronic Engineering
2017 - 2020
簡介
Study: -Machine Learning -Deep Learning -Data Mining -Computer Vision -Digital Signal Processing Coursework: -Brain MRI Segmentation using ResNet-V2 & Keras -CIFAR-10 challenge using Inception Network & Keras FYP: -Deep learning application in autonomous mobile robot
Master of Science (MS)
Electrical & Electronic Engineering
2011 - 2015
簡介
I studied 4 years covering the Bachelor and Master program FYP: -Work-stealing for ZYNQ FPGA Applied work-stealing principle to design multi-thread scheduler in C++ to offload CPU work to FPGA