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Benjamin Wan
Digital IC Design Engineer
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Benjamin Wan

Digital IC Design Engineer
Digital Design Engineer, have been working in IC Design for more than 3 years. Apart from the hardware design work, I also spend my time studying deep learning and robotics.
Allystar Technology Co. Ltd
The University of Hong Kong
Hong Kong

职场能力评价

专业背景

  • 目前状态
  • 专业
    数据工程师
  • 产业
  • 工作年资
    2 到 4 年
  • 管理经历
  • 技能
    C++
    Verilog HDL
    Python
    Tensorflow (Keras)
    Linux
  • 语言能力
    Chinese
    母语或双语
    English
    专业
  • 最高学历
    硕士

求职偏好

  • 预期工作模式
    全职
    对远端工作有兴趣
  • 希望获得的职位
    IC Design Engineer; FPGA Engineer; Deep Learning
  • 期望的工作地点
    Taipei, 台灣
  • 接案服务

工作经验

Digital IC Design Engineer

2018年3月 - 现在
-Worked for Baseband Technology Team of GPS SoC ASIC project -Designed Fast Fourier Transform accelerator -Used Python to design digital signal processing model for hardware design and testing -Used C to implement embedded software ROM code for baseband debug and performance test

Digital Design Engineer

2017年1月 - 2017年12月
1 年 0 个月
-Worked for Digital Design Team and helped to build LED display controller -Designed 2D graphics controller for on-screen display -Designed hardware bootloader for embedded processor

FPGA Design Engineer

2015年12月 - 2016年7月
8 个月
-Supported the development and testing of company products -Setup testing environment on ZYNQ Zedboard to evaluate Xilinx Video IP -Created control module of Xilinx Video IP for the integration of the IP into image scaler accelerator product

学历

Master of Science (MS)
Electrical & Electronic Engineering
2017 - 2020
简介
Study: -Machine Learning -Deep Learning -Data Mining -Computer Vision -Digital Signal Processing Coursework: -Brain MRI Segmentation using ResNet-V2 & Keras -CIFAR-10 challenge using Inception Network & Keras FYP: -Deep learning application in autonomous mobile robot
Master of Science (MS)
Electrical & Electronic Engineering
2011 - 2015
简介
I studied 4 years covering the Bachelor and Master program FYP: -Work-stealing for ZYNQ FPGA Applied work-stealing principle to design multi-thread scheduler in C++ to offload CPU work to FPGA